VHDL Mquina de Estados (FSM) 1 MC602 2011 Tpicos IC-UNICAMP - PowerPoint PPT Presentation

MC 602 IC-UNICAMP IC/Unicamp 2011s2 Prof Mario Côrtes VHDL Máquina de Estados (FSM) 1 MC602 – 2011

Tópicos IC-UNICAMP • Máquinas de estados – Moore – Mealy • Dois templates para implementação em VHDL 2 MC602 – 2011

Forma geral de um circuito síncrono IC-UNICAMP W Combinational Combinational Z Flip-flops circuit circuit Q Clock 3 MC602 – 2011

Máquina de Moore IC-UNICAMP Reset w = 1 w ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ = 0 A z = 0 B z = 0 w = 0 w w = 0 = 1 ⁄ ⁄ ⁄ ⁄ C z = 1 w = 1 Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0 4 MC602 – 2011

Diagrama de Estados IC-UNICAMP Rese t w = 1 w ⁄ ⁄⁄ ⁄ ⁄ ⁄⁄ ⁄ Next state = 0 A z 0 = B z 0 = Present Output w = 0 z state w = 0 w = 1 w w = 0 = 1 A A B 0 ⁄⁄ ⁄ ⁄ C z 1 = B A C 0 C A C 1 w = 1 5 MC602 – 2011

Implementação IC-UNICAMP Y y 1 1 w Combinational Combinational z circuit circuit Y y 2 2 Clock 6 MC602 – 2011

Atribuição de Estado IC-UNICAMP Next state Present Output w = 0 w = 1 state z y 2 y 1 Y 2 Y 1 Y 2 Y 1 A 00 00 01 0 B 01 00 10 0 C 10 00 10 1 dd dd d 11 7 MC602 – 2011

y y Derivação das expressões lógicas IC-UNICAMP 2 1 Ignoring don't cares Using don't cares w 00 01 11 10 0 0 0 d 0 Y 1 wy 1 y 2 Y 1 wy 1 y 2 = = 1 1 0 d 0 y 2 y 1 w 00 01 11 10 0 0 0 d 0 Y 2 wy 1 y 2 wy 1 y 2 Y 2 wy 1 wy 2 = + = + 1 w y 1 y 2 0 1 d 1 ( ) = + y 1 y 2 0 1 0 0 0 z y 1 y 2 z y 2 = = 1 1 d 8 MC602 – 2011

Circuito sequencial IC-UNICAMP Y y 2 2 z D Q Q Y y 1 1 w Q D Q Clock Resetn 9 MC602 – 2011

Timing diagram IC-UNICAMP t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 1 Clock 0 1 w 0 1 y 1 0 1 y 2 0 1 z 0 10 MC602 – 2011

FSM de Moore IC-UNICAMP USE ieee.std_logic_1164.all; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); -- Tipo Enumerado para -- definir os Estados SIGNAL y : State_type; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN -- A é o estado inicial y <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN con’t ... 11 MC602 – 2011

FSM de Moore IC-UNICAMP CASE y IS WHEN A => IF w = '0’ THEN y <= A; ELSE y <= B; END IF; WHEN B => IF w = '0’ THEN y <= A; ELSE y <= C; END IF; WHEN C => IF w = '0' THEN y <= A; ELSE y <= C; END IF; END CASE; END IF; END PROCESS; z <= '1' WHEN y = C ELSE '0'; END Behavior; 12 MC602 – 2011

FSM de Moore - Simulação IC-UNICAMP 13 MC602 – 2011

FSM de Moore - Simulação IC-UNICAMP 14 MC602 – 2011

FSM de Moore Codificação Alternativa (2 processos) IC-UNICAMP USE ieee.std_logic_1164.all; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); SIGNAL y_present, y_next : State_type; 15 MC602 – 2011

FSM de Moore Codificação Alternativa (2 processos) IC-UNICAMP BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A; ELSE y_next <= B; END IF; WHEN B => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; 16 MC602 – 2011

FSM de Moore - Codificação Alternativa IC-UNICAMP WHEN C => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; END CASE; END PROCESS; PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next; END IF; END PROCESS; z <= '1' WHEN y_present = C ELSE '0'; END Behavior; 17 MC602 – 2011

FSM - Especificando a Atribuição de Estados IC-UNICAMP ARCHITECTURE Behavior OF simple IS TYPE State_TYPE IS (A, B, C); ATTRIBUTE ENUM_ENCODING : STRING; ATTRIBUTE ENUM_ENCODING OF State_type: TYPE IS "00 01 11"; SIGNAL y_present, y_next : State_type; BEGIN con’t ... • Obs: Atributo Enum_Encoding é específico da ferramenta Quartus. Esta solução pode não funcionar em outras ferramentas CAD 18 MC602 – 2011

FSM - Especificando a Atribuição de Estados IC-UNICAMP LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY simple IS PORT ( Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END simple; ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A; ELSE y_next <= B; END IF; … con’t 19 MC602 – 2011

FSM - Especificando a Atribuição de Estados IC-UNICAMP WHEN B => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; WHEN C => IF w = '0' THEN y_next <= A; ELSE y_next <= C; END IF; WHEN OTHERS => y_next <= A; END CASE; END PROCESS; PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next; END IF; END PROCESS; z <= '1' WHEN y_present = C ELSE '0'; END Behavior; 20 MC602 – 2011

Máquina de Mealy IC-UNICAMP Reset w z ⁄ ⁄ ⁄ ⁄ = 1 = 0 w z w z ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ ⁄ = 0 = 0 = 1 = 1 A B w z ⁄ ⁄ ⁄ ⁄ = 0 = 0 21 MC602 – 2011

FSM de Mealy IC-UNICAMP LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mealy IS PORT (Clock, Resetn, w : IN STD_LOGIC; z : OUT STD_LOGIC ); END mealy; … con’t 22 MC602 – 2011

FSM de Mealy IC-UNICAMP ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B); SIGNAL y : State_type; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A; ELSE y <= B; END IF; WHEN B => IF w = '0' THEN y <= A; ELSE y <= B; END IF; END CASE; END IF; END PROCESS; … con’t 23 MC602 – 2011

FSM de Mealy IC-UNICAMP PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0'; WHEN B => z <= w; END CASE; END PROCESS; END Behavior; 24 MC602 – 2011