vertically integrated CMOS technology for vertexing applications L. - PowerPoint PPT Presentation

Monolithic and hybrid pixel sensors in vertically integrated CMOS technology for vertexing applications L. Ratti Università degli Studi di Pavia and INFN Pavia OUTLINE First test results from 3D DNW MAPS University of Bergamo and INFN Pavia characterization Luigi Gaioni, Massimo Manghisoni, • 3D technology Valerio Re, Gianluca Traversi • design features • characterization results University of Pavia and INFN Pavia Design of 3D monolithic and hybrid pixels for the Alessia Manazza, Stefano Zucca SuperB Factory

Vertex detectors in future HEP experiments Experiments at the future particle colliders (or upgrade of present colliders) will set severe requirements for silicon vertex trackers small amount of support low material budget material and interconnection low mass cooling power dissipation high functional vertical integration high granularity density small pixel technologies pitch data sparsification large hit rate small distance from digital-to-analog mixed-signal interference the interaction point chips large background in DNW MAPS, efficiency loss due to N-wells L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

The 3D-IC collaboration Several groups from US and Europe have been involved in the first 3D MPW for HEP (pixel and strip readout chips for ATLAS, CMS, B-factory, ILC) and photon science applications (X-ray imaging) ~ 3.2 cm Single set of masks used for both tiers to save money identical wafers produced by Chartered (now Globalfoundries) and face-to-face bonded by Tezzaron backside metallization by Tezzaron ~ 2.5 cm L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Tezzaron vertical integration (3D) technology TSV WB/BB pad In wafer-level, three-dimensional processes, multiple strata of planar devices are stacked and interconnected using through silicon vias (TSV) 3D processes rely upon the following enabling technologies Inter-tier Fabrication of electrically isolated connections bond pads through the silicon substrate (TSV formation) Substrate thinning (below 50 um) 1 st wafer Inter-layer alignment and mechanical/electrical bonding Tezzaron Semiconductor technology (via middle approach, vias are made between CMOS and BEOL) can be used to vertically integrate two 130 nm CMOS layers specifically processed by Globalfoundries Fabrication took quite a long time due to a number accidents both at the foundry and at the vertical integration facilities – the first 3D wafers became available by beginning of last summer L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

From 2D to 3D DNW MAPS Deep N-well monolithic pixels A large DNW is used to collect the charge released in the substrate A classical readout channel for capacitive detectors is used for Q-V conversion  gain decoupled from electrode capacitance NMOS devices of the analog section are built in the deep N-well Full CMOS for high performance analog and digital blocks  charge collection inefficiency depending on the relative weight of NW with respect to DNW What can be gained from going 3D sensor and analog front-end can be integrated in a different layer from the digital blocks less PMOS in the sensor layer  improved collection efficiency more room for both analog and digital power and signal routing Tier 1: collecting electrode and NMOS parts of the analog front-end (and a few PMOS) Tier 2: discriminator PMOS parts, digital front-end and peripheral digital readout electronics L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

3D DNW MAPS for the ILC vertex tracker Bunch structure of the ILC beam 20 um pitch monolithic pixel 0.95 ms 337 ns Sparsification based on a token passing scheme 0.2 s Double hit storage and double 5-bit time stamp register Digital readout x2820 Chip operation tailored on the ILC beam structure • detection phase, corresponding to the bunch train intertrain interval bunch train interval interval • readout phase, corresponding to the intertrain interval L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

DNW MAPS test structures Small test structures single pixels with and w/o detector emulating capacitor shunting the readout channel input (analog only) 3x3 DNW MAPS matrices (analog only, for charge collection tests) 8x8 and 16x16 DNW MAPS matrices (analog and digital, for readout architecture test) 1 st wafer ~ 5.2 mm metal + oxide +2 nd wafer substrate ~ 6.3 mm L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Analog front-end characterization Test of single channels and small matrices Peaking time of about 1 us, increasing with increasing input charge (as anticipated by simulations due to the non-linearity in the feedback network) DUT is located in the thick tier – signals Slew rate limitations on the rising edge in a number and power supply are fed through TSVs of samples and inter-tier bond pads L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Analog front-end characterization ENC: 35 - 40 electrons (good agreement with simulations) Estimated DNW capacitance: ~250 fF (about 25% larger than in circuit simulation) Charge sensitivity: ~700 mV/fC (~12% less than the design value) Input dynamic range: ~2000 electrons (good agreement with simulations) L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

DNW sensor test Collected charge as a function of the laser beam position Obtained by retro- illumination with an infrared laser Response to a laser pulse Some problems in getting more quantitative data on collection efficiency and charge sharing – laser beam is likely to be scattered from the irregular back-surface of the dice (which was not back-lapped) L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Digital readout Signals from an 8x8 matrix (detail of the first readout cells, f CK =20 MHz) TOKEN-IN (readout can start after the rising edge) READOUT-CK (clocks the serializer at the chip periphery) DATA-OUT (address and time-stamp, hit pixels read out serially) CELL-CK (one CELL-CK period is needed to read out a hit from one cell) Operation up to 50 MHz seems feasible L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Digital readout Signals from an 8x8 matrix (complete readout cycle, f CK =20 MHz) TOKEN-IN Npixel x Nbit x Tck = = 64 x 24 x 50 ns = 76.8 us TOKEN-OUT (readout stops on the rising edge) DATA-OUT During the test, all the pixel cells were always found to report a single hit (unless the MASTER-RESET signal is kept active during readout or the kill mask is used) L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

Layer misalignment wire bond wire bond pad pad Redundant inter-tier connection makes the signal path to and from the wire bond pads more robust level triggered always always set to 1 set to 1 (unless killed or reset) Single inter-tier connections between circuits on the two tiers – while the single sections work, misalignment by a single inter-tier pad makes the overall circuit non operable edge triggered never set to 1 L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

3D options for the SuperB SVT Layer0 Design of the SVT layer0 at SuperB has to comply with severe requirements large background, ~150 MHz/cm 2 (including a x5 safety factor), small thickness, <1% X 0 3D hybrid pixel detectors vertically integrated, mixed-signal circuit for a pixel detector in high resistivity silicon - fine pitch (50 μ m) bump bonding (IZM, Munich) or more advanced technologies (direct bonding by Ziptronix, or u-bump bonding by T-Micro) – based on a 130 nm dual tier CMOS process - 128x32 element chip to be submitted in the next run Direct bonding (Ziptronix) or u-bump bonding (T-Micro) 3D DNW MAPS sensors deep N-well sensors were proposed to enable fast readout through pixel-level sparsification and time stamping - DNW sensor in an undepleted substrate, analog front-end for capacitive detectors, analog and digital blocks integrated in separate layers – based on a 130 nm dual tier CMOS process - a 128x96 pixel chip is being designed for the next run L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011

3D front-end for hybrid pixels: the SuperPix1 chip polarity select TIER 1 TIER 2 shift-out shift-in C 2 C 1 THR A(s) DAC C F V GTHR 50 um pitch Polarity selection Power dissipation: 12 uW/pixel Threshold dispersion: 560/65 e - rms Peaking time: 250 ns (slightly (before/after correction) dependent on input charge) Digital section: in-pixel time-stamp, ENC=190 e - rms @C D =150 fF time-ordered triggered or data-push Charge sensitivity: 50 mV/fC readout L. Ratti , “Monolithic and hybrid pixel sensors in 3D CMOS technology”, 8 th Hiroshima Symposium, 5-8 December 2011