verilog 1 fundamentals
play

Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] - PowerPoint PPT Presentation

Nov 25, 2023 •447 likes •821 views

Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2,

  1. Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule 6.375 Complex Digital Systems Arvind Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-1

  2. Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-2

  3. Originally designers used breadboards for prototyping Number of Gates in Design 10 7 Solderless Breadboard 10 6 10 5 tangentsoft.net/elec/breadboard.html No symbolic 10 4 execution or testing 10 3 10 2 Printed circuit board 10 home.cogeco.ca Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-3

  4. HDLs enabled logic level simulation and testing Number of Gates Gate Level in Design Description 10 7 Simulate Test 10 6 Results Manual 10 5 10 4 10 3 10 2 HDL = Hardware Description Language 10 Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-4

  5. Designers began to use HDLs for higher level design Number of Gates Simulate Behavioral Test in Design Algorithm Results 10 7 Simulate 10 6 Test Register Results Transfer Level 10 5 Simulate 10 4 Test Gate Level Results 10 3 10 2 Manual 10 Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-5

  6. HDLs led to tools for automatic translation Number of Gates Simulate Behavioral Test in Design Algorithm Results 10 7 Manual Simulate 10 6 Test Register Results Transfer Level 10 5 Logic Synthesis Simulate 10 4 Test Gate Level Results 10 3 Auto Place + Route 10 2 HDLs: Verilog, VHDL… Tools: Spice, ModelSim, 10 DesignCompiler, … Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-6

  7. Raising the abstraction further … Number of Gates Simulate Guarded Atomic Test in Design Actions Results 10 7 GAA Compiler Simulate 10 6 Test Register Results Transfer Level 10 5 Logic Synthesis Simulate 10 4 Test Gate Level Results 10 3 Auto Place + Route 10 2 10 Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-7

  8. The current situation Behavioral RTL C, C++, MATLAB SystemC Verilog, VHDL, SystemVerilog Structural RTL Register Verilog, VHDL, Transfer Level SystemVerilog Logic Synthesis Simulators and other tools Gate Level are available at all levels but not compilers from the behavioral level to RTL Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-8

  9. Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-9

  10. Bit-vector is the only data type in Verilog A bit can take on one of four values Value Meaning 0 Logic zero 1 Logic one X Unknown logic value Z High impedance, floating An X bit might be a 0, 1, Z, or in transition. We can set bits to be X in situations where we don’t care what the value is. This can help catch bugs and improve synthesis quality. Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-10

  11. “wire” is used to denote a hardware net wire [15:0] instruction; Absolutely no type wire [15:0] memory_req; safety when wire [ 7:0] small_net; connecting nets! ? memory_req instruction instruction small_net Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-11

  12. Bit literals Binary literals 4’b10_11  8’b0000_0000  8’b0xx0_1xx1 Hexadecimal literals Underscores  32’h0a34_def1 are ignored  16’haxxx Base format (d,b,o,h) ‏ Decimal literals Decimal number  32’d42 representing size in bits We’ll learn how to actually assign literals to nets a little later Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-12

  13. Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-13

  14. Our Verilog Subset Verilog is a big language with many features not concerned with synthesizing hardware. The code you write for your processor should only contain the languages structures discussed in these slides. Anything else is not synthesizable, although it will simulate fine. Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-14

  15. A Verilog module has a name and a port list A B module adder( A, B, cout, sum ); 4 4 input [3:0] A; input [3:0] B; output cout; adder output [3:0] sum; // HDL modeling of 4 // adder functionality endmodule cout sum Note the semicolon at the end of the port Ports must have a list! direction (or be bidirectional) and a bitwidth Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-15

  16. Alternate syntax A B Traditional Verilog-1995 Syntax 4 4 module adder( A, B, cout, sum ); input [3:0] A; input [3:0] B; adder output cout; output [3:0] sum; 4 ANSI C Style Verilog-2001 Syntax cout sum module adder( input [3:0] A, input [3:0] B, output cout, output [3:0] sum ); Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-16

  17. A module can instantiate other modules A B adder FA FA FA FA cout S a b cin module adder( input [3:0] A, B, cout FA output cout, output [3:0] S ); c wire c0, c1, c2; module FA( input a, b, cin FA fa0( ... ); output cout, sum ); FA fa1( ... ); // HDL modeling of 1 bit FA fa2( ... ); // full adder functionality FA fa3( ... ); endmodule endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-17

  18. Connecting modules A B adder FA FA FA FA cout S module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); Carry Chain endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-18

  19. Alternative syntax Connecting ports by ordered list FA fa0( A[0], B[0], 1’b0, c0, S[0] ); Connecting ports by name (compact) FA fa0( .a(A[0]), .b(B[0]), .cin(1’b0), .cout(c0), .sum(S[0]) ); Argument order does not matter when ports are connected by name FA fa0 ( .a (A[0]), Connecting ports by name .cin (1’b0), yields clearer and less .b (B[0]), buggy code. .cout (c0), .sum (S[0]) ); Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-19

  20. Verilog Fundamentals History of hardware design languages Data types Structural Verilog Simple behaviors FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1’b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2], B[2], c1, c2, S[2] ); FA fa3( A[3], B[3], c2, cout, S[3] ); endmodule Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-20

  21. A module’s behavior can be described in many different ways but it should not matter from outside Example: mux4 Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-21

  22. mux4: Gate-level structural Verilog module mux4(input a,b,c,d, input [1:0] sel, output out); wire [1:0] sel_b; b d a c sel[1] sel[0] not not0( sel_b[0], sel[0] ); not not1( sel_b[1], sel[1] ); wire n0, n1, n2, n3; and and0( n0, c, sel[1] ); and and1( n1, a, sel_b[1] ); and and2( n2, d, sel[1] ); and and3( n3, b, sel_b[1] ); wire x0, x1; nor nor0( x0, n0, n1 ); nor nor1( x1, n2, n3 ); wire y0, y1; or or0( y0, x0, sel[0] ); or or1( y1, x1, sel_b[0] ); nand nand0( out, y0, y1 ); out Courtesy of Arvind http:// endmodule csg.csail.mit.edu/6.375/ L02-22

  23. mux4: Using continuous assignments Language defined module mux4( input a, b, c, d operators input [1:0] sel, output out ); wire out, t0, t1; assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) ); assign t1 = ~( (sel[1] & d) | (~sel[1] & b) ); assign t0 = ~( (sel[1] & c) | (~sel[1] & a) ); endmodule The order of these continuous assignment statements does not matter. They essentially happen in parallel! Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-23

  24. mux4: Behavioral style // Four input multiplexer module mux4( input a, b, c, d input [1:0] sel, output out ); assign out = ( sel == 0 ) ? a : ( sel == 1 ) ? b : ( sel == 2 ) ? c : ( sel == 3 ) ? d : 1’bx; endmodule If input is undefined we want to propagate that information. Courtesy of Arvind http:// csg.csail.mit.edu/6.375/ L02-24

Recommend

VERILOG Hardware Description Language CAD for VLSI 1 About Verilog Along with VHDL, Verilog

VERILOG Hardware Description Language CAD for VLSI 1 About Verilog Along with VHDL, Verilog

VERILOG Hardware Description Language CAD for VLSI 1 About Verilog Along with VHDL, Verilog is among the most widely used HDLs. Main differences: VHDL was designed to support system- level design and specification. Verilog was

833 views • 45 slides
Verilog Hung-Wei Tseng Verilog Verilog is a hardware description language (HDL). In this

Verilog Hung-Wei Tseng Verilog Verilog is a hardware description language (HDL). In this

Verilog Hung-Wei Tseng Verilog Verilog is a hardware description language (HDL). In this class, we use Verilog to implement and verify your processor. C/Java like syntax 2 Data type in Verilog Bit vector is the only data type in

319 views • 14 slides
CS6710 Tool Suite Verilog is the Key Tool Verilog Sim Behavioral Verilog is synthesized into

CS6710 Tool Suite Verilog is the Key Tool Verilog Sim Behavioral Verilog is synthesized into

CS6710 Tool Suite Verilog is the Key Tool Verilog Sim Behavioral Verilog is synthesized into Structural Verilog Synopsys Behavioral Synthesis Structural Verilog represents net-lists Verilog Structural From Behavioral Cadence

607 views • 21 slides
CS6710 Tool Suite Verilog is the Key Tool Verilog-XL Behavioral Verilog is synthesized into

CS6710 Tool Suite Verilog is the Key Tool Verilog-XL Behavioral Verilog is synthesized into

CS6710 Tool Suite Verilog is the Key Tool Verilog-XL Behavioral Verilog is synthesized into Structural Verilog Synopsys Behavioral Synthesis Structural Verilog represents net-lists Verilog Structural From Behavioral Cadence

403 views • 19 slides
CS6710 Tool Suite Verilog Sim Synopsys Behavioral Synthesis Verilog Structural Verilog

CS6710 Tool Suite Verilog Sim Synopsys Behavioral Synthesis Verilog Structural Verilog

CS6710 Tool Suite Verilog Sim Synopsys Behavioral Synthesis Verilog Structural Verilog Cadence Your Encounter Library Digital Impl. Circuit Verilog sim Layout Cadence Cadence LVS AutoRouter Virtuoso Composer Layout-XL Layout

899 views • 63 slides
CS6710 Tool Suite Verilog-XL Synopsys Behavioral Synthesis Verilog Structural Verilog

CS6710 Tool Suite Verilog-XL Synopsys Behavioral Synthesis Verilog Structural Verilog

CS6710 Tool Suite Verilog-XL Synopsys Behavioral Synthesis Verilog Structural Verilog Cadence Your SOC Encounter Library Circuit Verilog-XL CSI Layout Cadence Cadence LVS AutoRouter Virtuoso Composer Layout-XL Layout

811 views • 55 slides
Introduction*To*Verilog*for* Combinational*Logic

Introduction*To*Verilog*for* Combinational*Logic

Introduction*To*Verilog*for* Combinational*Logic Verilog*is*a*language*used*for*simulation*and* synthesis*of*digital*logic. A*New*Extension*System*Verilog*also*Supports* new*features*including*Verification*of*Digital*Systems

641 views • 13 slides
CS6710 Tool Suite Verilog-XL Synopsys Behavioral Design Compiler Verilog Structural Verilog

CS6710 Tool Suite Verilog-XL Synopsys Behavioral Design Compiler Verilog Structural Verilog

Synthesis and Place & Route Synopsys design compiler Cadence SOC Encounter CS6710 Tool Suite Verilog-XL Synopsys Behavioral Design Compiler Verilog Structural Verilog Cadence Your SOC Library Encounter Circuit Verilog-XL CSI

598 views • 30 slides
Today: More Verilog and Sequential Logic Today: More Verilog and Sequential Logic T Finit e St

Today: More Verilog and Sequential Logic Today: More Verilog and Sequential Logic T Finit e St

Today: More Verilog and Sequential Logic Today: More Verilog and Sequential Logic T Finit e St at e Machines and Verilog T Reasoning about Moore and Mealy machines S highlight -t he-arrows met hod T Example: Traf f ic Light Cont

327 views • 5 slides
Data Types Possible Values: 0: logic 0, false 1: logic 1, true X: unknown logic

Data Types Possible Values: 0: logic 0, false 1: logic 1, true X: unknown logic

Verilog for Testbenches A little Verilog Big picture: Two main Hardware Description Languages (HDL) out there VHDL Designed by committee on request of the Department of Defense Based on Ada Verilog Designed by a

357 views • 14 slides
CSSE 232 Computer Architecture I Verilog 1 / 10 What it is Verilog is hardware description

CSSE 232 Computer Architecture I Verilog 1 / 10 What it is Verilog is hardware description

CSSE 232 Computer Architecture I Verilog 1 / 10 What it is Verilog is hardware description language Describes the functions of a hardware circuit Can be used to test circuits also Looks similar to C ( + , - , != , ~ , etc)

510 views • 10 slides
Verilog 1 / 10 What it is Verilog is hardware description language Describes the functions

Verilog 1 / 10 What it is Verilog is hardware description language Describes the functions

Verilog 1 / 10 What it is Verilog is hardware description language Describes the functions of a hardware circuit Can be used to test circuits also Looks similar to C ( + , - , != , ~ , etc) Multiple parts can run in parallel (just

248 views • 10 slides
CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural

CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural

Synthesis and Place & Route Synopsys design compiler Cadence Encounter Digital Implementation System (EDI) CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural Verilog Cadence Your EDI Library

511 views • 36 slides
CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural

CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural

Synthesis and Place & Route Synopsys design compiler Cadence Encounter Digital Implementation System (EDI) CS/ECE 6710 Tool Suite Verilog sim Synopsys Behavioral Design Compiler Verilog Structural Verilog Cadence Your EDI Library

580 views • 46 slides
Verilog for Testbenches Overall Module Structure A little Verilog module name (args);

Verilog for Testbenches Overall Module Structure A little Verilog module name (args);

Verilog for Testbenches Overall Module Structure A little Verilog module name (args); Big picture: Two main Hardware begin parameter ; // define parameters Description Languages (HDL) out there input ; // define input

441 views • 5 slides
Today: Verilog and Sequential Logic Today: Verilog and Sequential Logic T Flip-f lops S

Today: Verilog and Sequential Logic Today: Verilog and Sequential Logic T Flip-f lops S

Today: Verilog and Sequential Logic Today: Verilog and Sequential Logic T Flip-f lops S represent at ion of clocks - t iming of st at e changes S asynchronous vs. synchronous T Count ers (St at e Machines) S st ruct ural view (FFs

394 views • 5 slides
Verilog for Testbenches Big picture: Two main Hardware Description Languages (HDL) out there

Verilog for Testbenches Big picture: Two main Hardware Description Languages (HDL) out there

Verilog for Testbenches Verilog for Testbenches Big picture: Two main Hardware Description Languages (HDL) out there VHDL Designed by committee on request of the DoD Based on Ada Verilog Designed by a company for their own

436 views • 18 slides
Introduction to Digital VLSI Design VLSI Verilog

Introduction to Digital VLSI Design VLSI Verilog

Introduction to Digital VLSI Design VLSI Verilog Logic Synthesis with Verilog HDL Lecturer: Gil Rahav Semester B , EE Dept. BGU. Freescale Semiconductors Israel 09/03/07 1 Objectives

970 views • 55 slides
Design and Verilog Module Creating a design and implementing in FPGA Design Verilog

Design and Verilog Module Creating a design and implementing in FPGA Design Verilog

Design and Verilog Module Creating a design and implementing in FPGA Design Verilog (mainly) Schematic(sometimes) Verify Need writing a testbench Simulation using ISIM Creating a design and implementing in FPGA Add User

276 views • 15 slides
CS6710 Tool Suite Verilog-XL Synthesis and Place & Route Synopsys Behavioral Design

CS6710 Tool Suite Verilog-XL Synthesis and Place & Route Synopsys Behavioral Design

CS6710 Tool Suite Verilog-XL Synthesis and Place & Route Synopsys Behavioral Design Compiler Verilog Structural Synopsys design compiler Verilog Cadence Cadence SOC Encounter Your SOC Library Encounter Circuit Verilog-XL CSI

389 views • 10 slides
VHDL/Verilog Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog

VHDL/Verilog Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog

VHDL/Verilog Simulation Testbench Design The Test Bench Concept Elements of a VHDL/Verilog testbench Unit Under Test (UUT) or Device Under Test (DUT) instantiate one or more UUTs Stimulus of UUT inputs algorithmic from

513 views • 32 slides
UMBC A B M A L T F O U M B C I M Y O R T 1 (10/24/05) I E S R C E O V

UMBC A B M A L T F O U M B C I M Y O R T 1 (10/24/05) I E S R C E O V

Programmable Logic Devices Verilog IV CMPE 415 Behavioral Descriptions We have already discussed 3 types of abstract (non-structural) behaviors in Verilog. continuous assignments Implement implicit combinational logic through static

461 views • 22 slides
VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3.

VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3.

VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3. Sequential and Parallel Blocks 4. Conditions and Loops in Verilog 5. Procedural Assignment 6. Timing controls 7. Combinatorial Logic in

736 views • 51 slides
CS/ECE 6710 Tool Suite Verilog sim Synthesis and Place & Route Synopsys Behavioral Design

CS/ECE 6710 Tool Suite Verilog sim Synthesis and Place & Route Synopsys Behavioral Design

CS/ECE 6710 Tool Suite Verilog sim Synthesis and Place & Route Synopsys Behavioral Design Compiler Verilog Structural Synopsys design compiler Verilog Cadence Cadence Encounter Digital Your EDI Implementation System (EDI) Library

398 views • 12 slides

More recommend