varying speed processor
play

Varying-Speed Processor Sanjoy Baruah and Zhishan Guo Department of - PowerPoint PPT Presentation

Scheduling Mixed-Criticality Implicit- Deadline Sporadic Task Systems upon a Varying-Speed Processor Sanjoy Baruah and Zhishan Guo Department of Computer Science, UNC Chapel Hill The Multi-WCET MC Task Model The Liu & Layland (LL)


  1. Scheduling Mixed-Criticality Implicit- Deadline Sporadic Task Systems upon a Varying-Speed Processor Sanjoy Baruah and Zhishan Guo Department of Computer Science, UNC Chapel Hill

  2. The Multi-WCET MC Task Model • The Liu & Layland (LL) sporadic task model: Task τ i = (c i , T i ) – Worst-case execution requirement – Minimum inter-arrival separation (period) Static Analysis • WCET-analysis tools may be more or less conservative • Example: x := a + b – 3 ~ 321 cycles c iHI c iLO t Measurement Based

  3. Other Dimensions -- Periods • The Liu & Layland (LL) sporadic task model: Task τ i = (c i , T i ) – Worst-case execution requirement – Minimum inter-arrival separation (period) • Time/Event-triggered periodic tasks – Fixed/Varying duration between executions – Minimum duration needs to be estimated – Estimations are more or less pessimistic for validating safety-critical or non-critical functions

  4. Other Dimensions -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip.

  5. Other Dimensions -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick.

  6. Other Dimensions -- CPU Speeds • Advanced hardware features – Main frequency is forced down when ambient temperature is too high, to prevent permanent damage to the chip. – Detect if signals are late at the circuit level; and recover by delaying next clock tick. • GALS: Globally Asynchronous Locally Synchronous – locally synchronous modules that communicate asynchronously – local clocks may be paused, stretched, or data-driven

  7. Previous Work • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – …

  8. Previous Work • Steve Vestal. Preemptive scheduling of multi-criticality systems with varying degrees of execution time assurance . RTSS 2007. • Alan Burns and Robert I. Davis. Mixed Criticality Systems - A Review . 4 th Ed., June 2014. http://www-users.cs.york.ac.uk/burns/review.pdf • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – …

  9. Previous Work • Sanjoy Baruah and Zhishan Guo. Mixed-criticality scheduling upon varying-speed processors . RTSS2013. – Job Set,& dual criticality level – Table driven & LP based – Optimal (w.r.t. processing speeds) • Zhishan Guo and Sanjoy Baruah. Implementing Mixed-criticality Systems Upon a Preemptive Varying-speed Processor. LITES, 1(2):3:1 - 3:19, 2014. – Multiple criticality levels + O(n log n) algorithm for the 2-level case • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – …

  10. This Work • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – … COMBINATION

  11. Alessandro Biondi, Alessandra Melani, Mauro Marinoni, Marco Di Natale, Giorgio Buttazzo, This Work Exact Interference of Adaptive Variable-Rate Tasks Under Fixed-Priority Scheduling , ECRTS 2014 • Example: Adaptive Variable-Rate Tasks – The task activation is triggered at specific rotation angles – Varying rotation speeds lead to varying WCETs & periods • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – … COMBINATION

  12. This Work • MC implicit-deadline sporadic tasks (multi-WCET) • Varying-speed uni-processor • Dual-criticality • Multiple dimensions to such MC modeling – upper bound on the execution time of code – lower bound on the processor speed – lower bound on duration between external interrupts (periods) – … COMBINATION

  13. Model - Varying-Speed Processor Clock frequency time

  14. Model - Varying-Speed Processor Clock frequency 1 ρ time Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ

  15. Model - Varying-Speed Processor Clock frequency 1 ρ time time Normal mode Degraded mode Non-functional

  16. Model - Varying-Speed Processor time Normal mode May switch mode 1 Degraded mode at any time ρ Non-functional

  17. Model - Varying-Speed Processor • It is not a priori known when, or whether, processor degradation and/or jobs exceeding their LO-WCET estimations will occur ( non-clairvoyant ). c iHI c iLO t time Normal mode May switch mode 1 Degraded mode at any time ρ Non-functional

  18. Problem • MC sporadic task set – LO-Criticality Behavior c iLO Each job signals completion without exceeding ; – HI-Criticality Behavior c iHI Each job signals completion without exceeding , some job does not signal completion after executing . c iLO • Varying-speed uni-processor Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ Normal mode Degraded mode Non-functional

  19. Correctness • MC sporadic task set – LO-Criticality Behavior c iLO Each job signals completion without exceeding ; – HI-Criticality Behavior c iHI Each job signals completion without exceeding , AND some job does not signal completion after executing . c iLO • Varying-speed uni-processor Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ Normal mode Degraded mode Non-functional

  20. Correctness • MC sporadic task set – LO-Criticality Behavior c iLO Each job signals completion without exceeding ; – HI-Criticality Behavior c iHI Each job signals completion without exceeding , some job does not signal completion after executing . c iLO • Varying-speed uni-processor OR Processor speed ≥ 1 Processor speed < 1 , but ≥ ρ Processor speed < ρ Normal mode Degraded mode Non-functional

  21. Contribution & Related work • EDF-VD – Originally designed for Multi-WCET only – [Baruah et al., European Symposium on Algorithms 2011] – [Baruah et al., ECRTS 2012] Extended • Multi-WCET + Varying-Speed Processor • VDF - Virtual Deadline First – Non-Monitoring: VDF-NM, VDF-NM+ – Self-Monitoring: VDF-WM – Correctness, Speedup, Schedulability Experiments Self-Monitoring : the processor “immediately” knows if and when degradation occurs.

  22. Algorithm - Overview • VDF - Virtual Deadline First – Prior to run-time • Schedulability test • Virtual deadlines are assigned proportionally to original deadlines with a common factor x ( 0< x <1 ) – During run-time • EDF -- assigned virtual deadlines • Revert to original deadlines when a HI-criticality behavior is detected , and drop LO-criticality tasks

  23. Algorithm - Example I c iLO c iHI p i (d i ) χ i τ LO 1 1 2 (2) LO ρ = 0.5, τ HI 2 3 10 (10) HI τ LO t 20 0 10 τ HI 0 10 t 20

  24. Algorithm - Example I c iLO c iHI p i (d i ’) χ i τ LO 1 1 2 (2) LO ρ = 0.5, x=0.4 τ HI 2 3 10 ( 4 ) HI τ LO t 20 0 10 τ HI 0 10 t 20

  25. Algorithm - Example I c iLO c iHI p i (d i ’) χ i τ LO 1 1 2 (2) LO ρ = 0.5, x=0.4 τ HI 2 3 10 ( 4 ) HI • During Run-Time – When NO HI-Criticality Behavior is detected… 0 10 t 13 20

  26. Algorithm - Example I c iLO c iHI p i (d i ’) χ i τ LO 1 1 2 (2) LO ρ = 0.5, x=0.4 τ HI 2 3 10 ( 4 ) HI • During Run-Time – When HI-Criticality Behavior is detected… HI-Criticality Behavior DETECTED at t=13 0 10 t 13 20 0 0 time time

  27. Algorithm - Monitor I c iLO c iHI p i (d i ’) χ i τ LO 1 1 2 (2) LO ρ = 0.5, x=0.4 τ HI 2 3 10 ( 4 ) HI • During Run-Time – When HI-Criticality Behavior is detected… HI-Criticality Behavior DETECTED at VDF-NM, VDF-NM+ t=13 for NON-MONITORING system 0 10 t 13 20 VDF-WM Self-Monitoring : the processor “immediately” knows if and when degradation occurs, which may lead to EARLIER detection of HI-Criticality Behavior

  28. Algorithm - VDF-NM & VDF-NM+ • VDF - Virtual Deadline First Task Set with – Prior to run-time Constrained Deadlines • Schedulability test • Virtual deadlines are assigned proportionally to original deadlines with a common factor x ( 0< x <1 ) VDF-NM : Density Based Schedulability Test VDF-NM+ : PTAS, for any desired degree of accuracy EDF-schedulability checked by binary search of x in (0,1) VDF-WM : Density Based Schedulability Test τ LO t τ HI t

  29. Experiments VDF-NM : VDF-NM+ : VDF-WM :

  30. Experiments VDF-NM : VDF-NM+ : VDF-WM :

  31. Experiments VDF-NM : VDF-NM+ : VDF-WM : x Among the 1000 generated task sets with utilizations of 0.7 , about 66% of them passed the schedulability test for VDF-WM.

  32. Experiments VDF-NM : VDF-NM+ : VDF-WM :

Recommend


More recommend