Tutorial Slides for Week 13 ENEL 353: Digital Circuits Fall 2014 - PowerPoint PPT Presentation

Tutorial Slides for Week 13 ENEL 353: Digital Circuits — Fall 2014 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 2 December, 2014

slide 2/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Topics for today Timing constraints for synchronous sequential logic. FSM design problems. Implementation of combinational logic with ROM circuits.

slide 3/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 1: Timing constraints, no clock skew CLK For registers, t setup = 25 ps, Q1 7:3 D2 7:3 C t hold = 10 ps, L D1 Q2 8 8 t pcq = 50 ps, Q1 2:0 D2 2:0 t ccq = 30 ps. R1 R2 Is there any possibility of a hold time violation at R2? If the desired T C is 500 ps, what constraints are there on the timing parameters of C L?

slide 4/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 2: Timing constraints with clock skew For registers, CLK1 CLK2 t setup = 25 ps, t hold = 10 ps, Q1 7:3 D2 7:3 t pcq = 50 ps, C L D1 Q2 8 t ccq = 30 ps. 8 Q1 2:0 D2 2:0 For C L , t pd = 350 ps, R1 R2 t cd = 200 ps. CLK1 and CLK2 come from the same source, with T C = 500 ps, but there may be some clock skew. What is the maximum t skew for reliable behaviour of R2? Suppose that buffers are available with t pd = 45 ps and t cd = 35 ps. How can they be used to allow the circuit to tolerate t skew = 70 ps?

slide 5/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 3: A simple counter design Produce a state transition diagram and a state transition table for a 2-bit “up/down” counter with two inputs A and B , with the following specification: A B behaviour 0 0 counter is frozen 0 1 count up (00 → 01 → 10 → 11 → 00) 1 0 reset to 00 1 1 count down (00 → 11 → 10 → 01 → 00) (Assume that the DFFs you have do not have reset inputs, so reset has to be done using a bit pattern on A and B .)

slide 6/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 4: A tricky counter design Suppose a circuit for the counter from Exercise 3 is ready. Show how to use that, one more DFF, and some combinational gates to make a counter with a 2-bit output that cycles through the sequence 00, 01, 10, 11, 10, 01, 00, 01, . . . CLK A S 1 B S 0 Remark: This is an example of factored FSM design.

slide 7/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 5: Using a ROM array for combinational logic Old-school microprocessor kits used 7-segment displays to display numbers in hexadecimal format. a f b g e c d Let’s design a ROM circuit that takes a 4-bit unsigned integer as input, and outputs the appropriate 7-bit signal to a 7-segment display.

slide 8/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Bus multiplexers An N :1 M -bit bus multiplexer is a straightforward and very useful extension of the multiplexer circuits we have seen already in ENEL 353. Data from one of N M -bit input buses, is copied to an M -bit output bus, according the value of one or more select inputs. Here is a 2:1 2-bit example . . . S � B 1:0 B 1 0 if S = 0 B 0 Y 1:0 = Y 1 C 1:0 if S = 1 Y 0 C 1 1 C 0

slide 9/9 ENEL 353 F14 T02 Tutorial Slides for Week 13 Exercise 6: A 4-input, 2-output ROM problem Suppose you are asked to implement the following logic using a ROM array: Y 1 ( B 3 , B 2 , B 1 , B 0 ) = Σ( m 0 , m 3 , m 4 , m 7 , m 10 , m 12 , m 15 ) Y 0 ( B 3 , B 2 , B 1 , B 0 ) = Σ( m 1 , m 2 , m 5 , m 12 , m 13 , m 14 ) What are the “natural” dimensions for the ROM array? Suppose you have only an 8 × 4 ROM array and a 2:1 2-bit bus multiplexer. Show how you can implement the given logic functions using those two circuit elements. Remark: This solution provides some hints about how memory array designers produce arrays that are “close to square,” instead of “way too deep but not very wide.”