Tutorial Slides for Week 10 ENEL 353: Digital Circuits Fall 2015 - PowerPoint PPT Presentation

Tutorial Slides for Week 10 ENEL 353: Digital Circuits — Fall 2015 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 10 November, 2015

slide 2/11 ENEL 353 F15 Tutorial Slides for Week 10 Topics for today D flip-flops and finite state machines.

slide 3/11 ENEL 353 F15 Tutorial Slides for Week 10 Exercise 1: Moore FSMs and the clock divider This is the general structure of a Moore FSM . . . CLK M next next inputs k k N state state output state outputs logic logic And this is a clock divider circuit . . . CLK Y

slide 4/11 ENEL 353 F15 Tutorial Slides for Week 10 The clock divider circuit is just about the simplest possible Moore FSM. For the clock divider, ◮ What is M , the number of input bits? ◮ What is k , the number of state bits? ◮ What is N , the number of output bits? ◮ What is correct Boolean algebra for the next-state logic? ◮ What is correct Boolean algebra for the output logic?

slide 5/11 ENEL 353 F15 Tutorial Slides for Week 10 Notes about notation for FSMs Your ENEL 353 instructors will follow notation used in the course textbook. S0, S1, S2 and so on are names of states . Note that the numbers are the same size as the S, on the same level. S 0 , S 1 , S 2 and so on are state bits — Q outputs of DFFs. Note that the numbers are subscripts . S ′ i is the next value of the state bit S i . Many books use the ′ operator for NOT. (For example, in those books A ′ means what our textbook would write as A .) Watch out for that! In discussion of FSMs, some books use Q i for the i th state bit, and Q ⋆ i for the next value of Q i .

slide 6/11 ENEL 353 F15 Tutorial Slides for Week 10 Exercise 2 For this Moore FSM, what are ◮ M , the number of inputs? CLK ◮ k , the number of state S ′ S 0 0 A bits? S ′ S 1 1 ◮ the number of possible S ′ S 2 states of the machine? 2 Y r ◮ N , the number of output bits? ◮ next-state equations? R ◮ output equations?

slide 7/11 ENEL 353 F15 Tutorial Slides for Week 10 Exercise 2, continued CLK Let’s add waveforms for S 0 , S ′ S 0 0 A S 1 and S 2 to the timing S ′ S 1 1 diagram. S ′ S 2 2 Let’s assume synchronous Y r reset for the three DFFs in the register. R 1 CLK 0 1 R 0 1 A 0

slide 8/11 ENEL 353 F15 Tutorial Slides for Week 10 Remark about Exercise 2 We found the waveforms for S 0 , S 1 and S 2 based on rules about the behaviour of DFFs. Next week in lectures, we’ll see another method for solving the problem. The textbook calls this method, “Deriving an FSM from its schematic.” Your instructors might sometimes call it “FSM analysis.”

slide 9/11 ENEL 353 F15 Tutorial Slides for Week 10 Exercise 3: More DFF practice CLK Q 0 Q 1 Q 2 A r r r R Let’s add waveforms for Q 0 , Q 1 and Q 2 to the timing diagram. 1 CLK 0 1 R 0 1 A 0

slide 10/11 ENEL 353 F15 Tutorial Slides for Week 10 Exercise 4: Simple FSM design Design an FSM with a single output bit, such that ◮ on reset the output goes to 0; ◮ when reset is turned off, the output repeats the sequence of 0 for one clock cycle, 1 for three cycles, 0 for one cycle, 1 for three cycles, and so on.

slide 11/11 ENEL 353 F15 Tutorial Slides for Week 10 Next week Tue Nov 17: Quiz #4—exact topics to be announced closer to the date of the quiz. Likely topics include SR latches, D latches, DFFs, and simple FSM designs. The Problem Set #4 exercises on sequential logic are highly recommended as preparation.