Towar ards Decr ds Decrypting ypting the Ar the Art of t of A Analo nalog g Lay Layout: out: Placement Placement Quality Quality Pr Prediction ediction via via Transf ansfer er Lear Learning ning Mingjie Liu *, Keren Zhu*, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z. Pan Dept. of Electrical and Computer Engineering The University of Texas at Austin * Indicates equal contributions.
2 Outline Outline • Introduction and Motivation • UT-AnLay Dataset with MAGICAL • Placement Quality Prediction • Improved Data Efficiency with Transfer Learning • Conclusions
3 Outline Outline • Introduction and Motivation • UT-AnLay Dataset with MAGICAL • Placement Quality Prediction • Improved Data Efficiency with Transfer Learning • Conclusions
4 Analog/Mixed Analog/Mixed-Signal Signal IC IC Demand Demand • High demand of analog/mixed-signal (AMS) IC in emerging applications Advanced computing Communication Healthcare Automotive Image Sources: IBM, Ansys, public technology
5 Analog/Mixed-Signal Analog/Mixed Signal IC IC Design Design Challenges Challenges • Repetitive iterations and feedback during manual design flows • Close interactions with circuit designers Front-end Electrical and layout engineers Design • Our focus is on back-end physical design (layout) stage • Provide design closure and guarantee to Back -end Physical meet specification , manufacturability, Design reliability, etc…
6 Challenges Challenges in in Analog Analog Layout Design Layout Design • Multiple performance trade-offs • No uniform representation for performance • Each design is “unique” • Complex layout dependent effects • BSIM4 model >250 parameters • Increased parasitic • Well proximity effect (WPE), substrate noise coupling, etc … • Complex layout design rules Behzad Razavi, 2000
7 Prior Prior Wor ork on k on Analog Analog Lay Layout out • Sensitivity analysis based optimization: ✓ Model how parasitic effects performance ✓ Some guarantee on performance × Simulations are too expensive for systems • Heuristic constraint based: How can we guide the back- ✓ Encode in layout algorithms end physical design process to ensure post-layout ✓ Enforced satisfiability for crucial effects: symmetry performance? × Difficult to enumerate × No room for trade-offs: contradictory constraints × Limited guarantee towards performance
8 Prior Prior Wor ork on k on Analog Analog Lay Layout out WellGAN [Xu et al., DAC, 2019] GeniusRoute [Zhu et al., ICCAD, 2019] • Leveraging generative neural network × Data hungry algorithms × Good human layout examples × Technology dependent: difficult to share data × No explicit optimization on performance
9 Decr Decrypting the ypting the Ar Art of t of Analog Analog Lay Layout out • “The process of constructing layouts for analog and mixed signal circuits have stubbornly defied all attempts at automation.” [Hastings, The Art of Analog Layout, 2001] • Our contributions: • A model for placement quality prediction for fast design space explorations • Automatically generated simulated layout training data with MAGICAL • 3D convolutional neural network with coordinate channel embeddings • Leveraging transfer learning for improved data efficiency • Open-sourced on GitHub: https://github.com/magical-eda/UT-AnLay
10 Outline Outline • Introduction and Motivation • UT-AnLay Dataset with MAGICAL • Placement Quality Prediction • Improved Data Efficiency with Transfer Learning • Conclusions
11 MA MAGICAL GICAL Lay Layout System out System • Input: unannotated netlist M A G I C A L M A G I C A L VA LI D ATI O N I N P U TS LA LAY O U T C O N STR A I N T EX TR A C TO R • Output: GDSII Layout & C i r cui t N et l i st Pat t ern M at chi ng + EVA LU ATI EV O N Sm al l Si gnal Anal ysi s • Key Components: D esi gn R ul es • Device Generation P LA C ER R O U TER M A G I C A L • Constraint Extraction O U TP U T Anal yt i cal Pl acem ent D EVI C E M ul t i -pi n G D SI I Layout G EN ER ATO R • Analog Placement A* Sear ch Post -Pl acem ent Par am et r i c • Analog Routing O pt i m i zat i on I nst ances • Fully-automated (no-human-in-the-loop) • Guided by analytical, heuristic, and machine learning algorithms • Open-sourced on GitHub: https://github.com/magical-eda/MAGICAL
12 Anal Analytical ytical Global Global Placement Placement • Objective: 𝑧 𝑦 𝑃𝑐𝑘𝑓𝑑𝑢𝑗𝑤𝑓 = 𝑔 𝑋𝑀 + 𝑏 ∙ 𝑔 𝑃𝑀 + 𝑐 ∙ 𝑔 𝐶𝑂𝐸 + 𝑑 ∙ 𝑔 + 𝑔 𝑇𝑍𝑁 𝑇𝑍𝑁 • Performance: • Wirelength term (half-perimeter wirelength): 𝑔 𝑋𝑀 = Σ 𝑜 𝑙 (max 𝑗∈𝑜 𝑙 𝑦 𝑗 − min 𝑗∈𝑜 𝑙 𝑦 𝑗 + max 𝑗∈𝑜 𝑙 𝑧 𝑗 − min 𝑗∈𝑜 𝑙 𝑧 𝑗 ) • Relaxed Constraints: 𝑔 𝑃𝑀 : Device overlap cost 𝑔 𝐶𝑂𝐸 : 𝑀𝑏𝑧𝑝𝑣𝑢 𝑐𝑝𝑣𝑜𝑒𝑏𝑠𝑧 𝑑𝑝𝑡𝑢 𝑧 𝑦 𝑔 , 𝑔 : 𝐸𝑓𝑤𝑗𝑑𝑓 𝑡𝑧𝑛𝑛𝑓𝑢𝑠𝑧 𝑑𝑝𝑜𝑡𝑢𝑠𝑏𝑗𝑜𝑢 𝑇𝑍𝑁 𝑇𝑍𝑁
13 • Wirelength term (half-perimeter wirelength): 𝑔 𝑋𝑀 = Σ 𝑜 𝑙 (max 𝑗∈𝑜 𝑙 𝑦 𝑗 − min 𝑗∈𝑜 𝑙 𝑦 𝑗 + max 𝑗∈𝑜 𝑙 𝑧 𝑗 − min 𝑗∈𝑜 𝑙 𝑧 𝑗 ) × Not a good indication of performance × Different nets should have different importance 𝑔 𝑋𝑀 = Σ 𝑜 𝑙 α 𝑜 𝑙 (max 𝑗∈𝑜 𝑙 𝑦 𝑗 − min 𝑗∈𝑜 𝑙 𝑦 𝑗 + max 𝑗∈𝑜 𝑙 𝑧 𝑗 − min 𝑗∈𝑜 𝑙 𝑧 𝑗 ) • Different penalty term indicating net criticality • Allow multiple layout solutions for same schematic
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15 • UT-AnLay Dataset: • Industrial level parasitic extraction and simulation tool • Custom designed testing benchmark suite • Over 16,000 different layout for each design Design Stage Compensation Layouts OTA1 3 Nested Miller 16376 OTA2 3 Nested Miller 16381 OTA3 2 Miller 16384 OTA4 2 None 16363
16 • UT-AnLay Dataset: • Circuit netlist • Device boundary box • Device placement coordinates (with pin coordinates) • Post layout simulation results X Routing information X Currently only OTA circuits X Currently only in TSMC 40nm technology
17 • UT-AnLay Dataset: • Noticeable difference in layout implementations • High variations in some performance • CMRR and offset -> Large variation • Gain, power, phase margin etc. -> Small variation
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19 Offset （ mV) Offset (mV) ~ 0 5.0 CMRR (dB) 110 CMRR (dB) 76.3
20 Outline Outline • Introduction and Motivation • UT-AnLay Dataset with MAGICAL • Placement Quality Prediction • Improved Data Efficiency with Transfer Learning • Conclusions
21 • Traditional automated analog layout generators • Human in the loop • Infer new heuristics and constraints • Poor generalizability and little flexibility New Heuristics /Constraints Placement Routing Extraction Simulation
22 • Design exploration and early design pruning • Generating layout is “cheap” • Verifying functionality is expensive • Predict performance in early design stage Explore new design Placement Downstream
23 • Define layout quality with post layout simulation ⚫ Layout sensitive performance: CMRR and offset • Formulate problem into binary classification ⚫ Balanced: Worst 25% vs Best 25% ⚫ Imbalanced: Worst 25% vs Rest 75%
24 • Placement feature extraction: • Device location and size: images • Circuit topology: separating devices to different channels • Device types: image intensity • Pin location: routing congestion map
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26 • Coordinate channel embedding • Additional channel for numerical coordinates [R. Liu et al., NIPS, 2018] • 3D CNN • Depth-wise convolution • Interactions between different channels [S. Ji et al., IEEE T. Pattern Anal, 2013
27 • Dataset: OTA1 with balanced labeling • Feature is of utmost importance • 3D CNN helps a little with generalization
28 Outline Outline • Introduction and Motivation • UT-AnLay Dataset with MAGICAL • Placement Quality Prediction • Improved Data Efficiency with Transfer Learning • Conclusions
29 Train Source Model Source Domain f s : X s -> Y s (x s , y s ) Initialize Fine-tune Target Domain Source Model (x s , y s ) f t : X t -> Y t • Transfer learning: • Train model on source domain with abundant data • Fine-tune model on target domain with limited data
30 • Source Domain: OTA1 • Target Domains: • OTA2: Same schematic and performance metric different sizing • OTA3: Different schematic same performance metric • OTA4: Different schematic and performance metric • Data utilization α : • Percentage of available training data in target domain • 20% reserved for testing α max = 0.8
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