Today � Power management � Hardware capabilities � Software management strategies
Power and Energy Review � Energy is power integrated over time � 1 Watt == 1 Joule / second � Heat depends on power consumption � Battery life depends on energy consumption � Both power and energy consumption must be bounded
The Power Problem � Processors are getting faster but using more power � Performance / Watt remains low � Battery capacities increase slowly � Solutions: � Use a better VLSI process � Have the system do less work � Spread work across several smaller, slower processors � Push the problem to the user • New cell phones often have worse lifetime than the previous generation • Most users choose features over lifetime! � Use power management techniques
Batteries � Usable energy density increasing by ~10% / year � Dominant rechargeable battery technology where energy density is important: Lithium-ion � 110-160 Wh/KG � About 1/3 the energy density of dynamite! � In contrast… � Gasoline: 14,000 Wh/Kg � Hydrogen: 38,000 Wh/Kg
CMOS Power Consumption � Affected by: � Voltage • Power consumption proportional to V 2 � Toggling • More activity == more power � Leakage • Idle components draw power
Power Saving Features � Voltage � Reduce power supply voltage � Toggling � Reduce activity � Use simpler hardware � These necessitate clock speed reductions � Leakage � Disconnect inactive parts from power supply
Clock Gating � Applicable to processors, memories, etc � Not analog components � Disconnect parts from clock when not in use � Stops signal propagation � Pros: � Simple � Fast – Stopping only clock distribution, not clock generation � Cons: � Clock still runs, using power � Does not prevent leakage
Supply Shutdown � Disconnect parts from power supply when not in use � Pros: � General � Saves the most power � Con: � Long transition time
Example: Intel SA-1100 � StrongARM variant for PDA-type devices � Small I- and D-caches � Runs up to 200 MHz � Three power modes � Run – normal operation � Idle – stops processor clock, I/O logic still powered � Sleep – most chip activity shut down
SA-1100 Sleep � Run → Sleep � 30 µs – Flush CPU state to RAM � 30 µs – Reset processor state � 30 µs – Shut down clock � Sleep → Run � 10 ms – Ramp up power supply � 150 ms – Stabilize clock � Small – Boot CPU
SA 1100 Transition Costs P = 400 mW Run 10 us 160 ms 10 us 90 us Idle Sleep 90 us P = 50 mW P = 0.16 mW � Power consumption during transition = P run
MCF5223x Power � Most peripherals can be independently powered down � CPU modes: run, wait, doze, stop � STOP instruction puts a running processor into one of the three power-saving modes • Which one depends on contents of LPCR � Interrupt can bring the CPU out of wait, doze, and stop � No recovery time to bring CPU, SRAM, and flash out of any power saving mode • PLL continues to run in all three modes
More MCF5223x � Run mode – 75-290 mA @ 25 MHz � Wait mode – 16 mA � CPU and memory clocks are stopped � Peripherals continue to operate normally � Doze mode – 16 mA � Some peripherals are stopped, others keep running � Stop mode – 0.2-10 mA � All clocks stopped – peripherals do not operate � Only external interrupts can wake the processor
Dynamic Voltage Scaling � Power is proportional to V 2 � Reduce power supply voltage → Save energy � Lower voltage necessitates reduced clock frequency � So we can trade off performance and lifetime on a set of batteries � Why dynamic? � Observation: Often, peak CPU requirement >> average CPU requirement � So: Run fast when we have to, run slow otherwise
More DVS � Changing voltage takes time � To stabilize power supply and clock � Both continuous and discrete DVS exist
DVS Examples � SA-1100 takes two voltages � 3.3 V and 1.5 V � AMD K6-2 � 8 frequencies 200-600 MHz � 1.4 V and 2.0 V � 0.4 ms for voltage change
DVS Capability Summary � In the general case we have: � Some set of voltage choices � Some set of frequency choices • For each frequency where is a minimum voltage that works � Some set of power saving modes � Some set of transition costs • Between frequencies • Between voltages • Between running and power saving modes � These are all low-level mechanisms – A high-level policy is needed
Power Management Policies � Static power management – Does not depend on system activity � E.g., user-initiated suspend, hibernate, etc. � Dynamic power management – Automatically take actions based on system activity � E.g. shut down functional units, change CPU frequency
Dynamic Power Management � Goal � Appropriately trade off between performance and power consumption � Basic premises � Systems have non-uniform workloads � It is possible to predict fluctuation in workload with some degree of accuracy • E.g., “the CPU was very busy for the past 1 ms, so it will probably remain busy for the next 1ms”
Problem Formulations � Need to figure out what the goal is � For example: � Minimize power under performance constraints • E.g. must not skip frames while playing MP3 or DVD � Maximize performance under power constraints • E.g. battery must last for the entire plane flight
Baseline Policy: Greedy � Immediately sleep or idle the processor when there’s no work to do � Works well when transition times are short compared to idle periods � Works poorly when transition times are relatively long • I.e., Run/Sleep transitions for the SA-1100 � Need to do better than this…
Break-Even Time T BE � Minimum idle time needed to make up for the cost of entering a sleep mode � Only beneficial to sleep the CPU if the idle time is longer than this � Assume for now that… � No performance penalty is tolerated � We know in advance the duration of idle periods
Break-Even Time � P TR : Power consumption during transition � P On : Power consumption when active � Assume P TR ≤ P On � T BE of an inactive state is the total time for entering and leaving the state � T BE = T TR = T On,Off + T Off,On � Example: � T BE = 160 ms + 90 μ s for SLEEP in SA-1100
How to Save Energy � Given an idle period T idle > T BE � Saved energy = (T idle - T TR )(P On - P OFF ) + T TR (P On – P TR ) � Total energy that can be saved depends on distribution and size of idle times
Power Saved � On real-world traces
Practical Power Saving � In real life we don’t know the duration of idle times in advance � Solutions: � Use a fixed timeout – go to sleep after some amount of time � Predict idle times based on past history � Also very important: � Disk, display, network interface, memory all use power � Need to manage these as well • E.g. shut down half the cache for apps with small working sets
Power and Energy � Reducing energy usage while providing advanced features is a big problem for portable embedded systems � Lots of implementation choices � Leads to difficult system design problems � Clever power management schemes are often annoying
Summary � Computing needs are increasing rapidly � Battery capacities are increasing slowly � Clever power management schemes can help � But too much cleverness is bad � Long-term solutions � Get help from the user � HW accelerators for demanding application kernels � Better power supplies
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