TLBs 3 one or two pages in each area? small areas of memory active - PowerPoint PPT Presentation

TLBs 3 one or two pages in each area? small areas of memory active at a time Code + Constants Writable data Heap / other dynamic Stack Used by OS 0x0000 0000 0040 0000 0x7F… 0xFFFF 8000 0000 0000 0xFFFF FFFF FFFF FFFF program memory active sets not acceptable 1 so add 8 cycles to each memory access? L1 cache hits — typically a couple cycles each? four-level page tables — four cache accesses per memory access cache accesses and multi-level PTs 2 keep getting new sets of problems until you get it right submitting only right and blank answers — doesn’t count as attempt 3 attempts per set of problems answer: 2-byte values read (or replaced) or “fault” page tables with 1-byte page entries random memory image memory HW 4

needed page table entries are very small page table entries and locality virtual page numbers not much spatial locality between page table entries (they’re used for kilobytes of data already) few active page table entries at a time enables highly associative cache designs 6 page table entry cache caled a TLB (translation lookaside bufger) very small cache of page table entries L1 cache TLB physical addresses bytes from memory only caches the page table lookup itself page table entries tens of bytes per block one page table entry per block usually thousands of blocks usually tens of entries only caches the page table lookup itself (generally) just entries from the last-level page table not much spatial locality between page table entries (they’re used for kilobytes of data already) few active page table entries at a time enables highly associative cache designs (generally) just entries from the last-level page table usually tens of entries page table entries have excellent temporal locality usually thousands of blocks typically one or two pages of the stack active typically one or two pages of code active typically one or two pages of heap/globals active 5 page table entries and locality page table entries have excellent temporal locality typically one or two pages of the stack active typically one or two pages of code active typically one or two pages of heap/globals active 5 page table entry cache caled a TLB (translation lookaside bufger) very small cache of page table entries L1 cache TLB physical addresses virtual page numbers bytes from memory page table entries tens of bytes per block one page table entry per block 6 each page contains whole functions, arrays, stack frames, etc. each page contains whole functions, arrays, stack frames, etc. needed page table entries are very small

page table entry cache address 0x10000 11 0101 01 00 1101 1111 TLB and the MMU (2) 7 program from TLB base register L1 Cache/Memory (‘page table walk’ logic) MMU TLB and the MMU (1) 6 enables highly associative cache designs page table TLB caled a TLB (translation lookaside bufger) physical address but no need to store invalid PTEs in TLB need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access virtual address 00 1101 1111 + cause fault? split PTE parts and kernel bit check valid 1101 0011 11 data or instruction cache few active page table entries at a time (they’re used for kilobytes of data already) not much spatial locality between page table entries tens of bytes per block not much spatial locality between page table entries (generally) just entries from the last-level page table only caches the page table lookup itself usually tens of entries usually thousands of blocks one page table entry per block page table entries few active page table entries at a time bytes from memory virtual page numbers physical addresses TLB L1 cache very small cache of page table entries (they’re used for kilobytes of data already) enables highly associative cache designs (generally) just entries from the last-level page table bytes from memory only caches the page table lookup itself usually tens of entries usually thousands of blocks one page table entry per block tens of bytes per block page table entries virtual page numbers 6 physical addresses TLB L1 cache very small cache of page table entries caled a TLB (translation lookaside bufger) page table entry cache 8 × PTE size

TLB and the MMU (2) split PTE parts need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access virtual address physical address 00 1101 1111 cause fault? and kernel bit 8 check valid 1101 0011 11 data or instruction cache + TLB base register page table 0x10000 but no need to store invalid PTEs in TLB TLB and the MMU (2) 11 0101 01 00 1101 1111 cause fault? but no need to store invalid PTEs in TLB need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access virtual address physical address 00 1101 1111 split PTE parts 11 0101 01 00 1101 1111 and kernel bit check valid 1101 0011 11 data or instruction cache + TLB base register page table 0x10000 11 0101 01 00 1101 1111 TLB and the MMU (2) 8 cause fault? but no need to store invalid PTEs in TLB need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access virtual address physical address 00 1101 1111 split PTE parts but no need to store invalid PTEs in TLB and kernel bit check valid 1101 0011 11 data or instruction cache + TLB base register page table 0x10000 8 TLB and the MMU (2) 11 0101 01 00 1101 1111 and kernel bit need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access virtual address physical address 00 1101 1111 cause fault? split PTE parts check valid 1101 0011 11 data or instruction cache + TLB base register page table 0x10000 8 × PTE size × PTE size × PTE size × PTE size

TLB and the MMU (2) physical … … … … … write … page # physical valid tag write … page # valid tag … TLB organization (2-way set associative) 10 entry table page is hit? OR page table entry AND AND tag = … … 11 0101 01 00 1101 1111 (program address) entry table page is hit? OR page table entry AND AND tag = = index … 010110 11 100 1 0x12F 11 1 1 0x123 10 1 … = (program address) index virtual address 9 means TLB output can be used directly to form address doesn’t matter which last-level page table TLB caches valid last-level page table entries TLB and multi-level page tables 8 but no need to store invalid PTEs in TLB need to check permissions (read/kernel/etc.) TLB miss: TLB gets a copy of the page table entry TLB miss: page table access happens TLB hit: TLB accesses replaces page table access physical address 010110 00 1101 1111 cause fault? split PTE parts and kernel bit check valid 1101 0011 11 data or instruction cache + TLB base register page table 0x10000 TLB organization (2-way set associative) valid tag physical page # 11 100 1 0x12F 11 1 1 0x123 10 1 … … … … write … valid tag physical page # write … … … … … … … 10 × PTE size VPN page ofgset VPN page ofgset

TLB organization (2-way set associative) valid tag … … … … … … … write … page # physical valid tag write … page # physical TLB organization (2-way set associative) … AND 010110 index (program address) = = tag AND 10 page table entry OR is hit? page table entry … … valid tag address splitting for TLBs (1) OR is hit? page table entry 10 my desktop: AND 64-entry, 4-way L1 data TLB TLB index bits? sets — 4 bits TLB tag bits? bit virtual address — bit TLB tag page table entry AND 1 1 10 0x123 1 1 11 0x12F 100 tag 11 010110 index (program address) = = 11 100 1 1 10 0x123 1 1 11 0x12F 100 … 11 010110 index (program address) = = 1 … AND write … physical page # write … valid tag physical page # … … … … … … … … 0x12F tag AND … … … … … … … … page table entry 1 10 0x123 1 1 11 … … write … TLB organization (2-way set associative) OR is hit? page table entry page # 10 valid tag physical page # write … valid tag physical 11 VPN page ofgset VPN page ofgset VPN page ofgset 4KB ( 2 12 byte) pages; 48-bit virtual address