CS533 Concepts of Operating Systems Jonathan Walpole
The Structure of the “ THE ” -Multiprogramming System Edsger W. Dijkstra Technological University, Eindhoven, The Netherlands Communications of the ACM, 11(5):341--346, 1968
System Hardware Electrologica X8 32K core memory, 2.5 µ sec 512K word drum, 1024 words per track, … Indirect addressing Interrupt mechanism “to die for” Low capacity channels, 10 are used 3 paper tape readers at 1000 char/sec 3 paper tape punches at 150char/sec 2 teleprinters 1 plotter 1 line printer
Goals Process a continuous flow of user programs Reduce turn-around time for short programs Economic use of peripheral devices and CPU Automatic control of backing store Efficient use of the machine for multiple applications Not intended as a multi-user interactive system
Paged Virtual Memory Hardware memory units – core pages and drum pages Information units – segments (virtual pages) - a segment fits in a page - segment identifier gives fast access to a segment variable - segment variable value tells if the segment is empty or not - if the segment is not empty, the value denotes which page(s) the segment can be found in A program does not have to occupy consecutive drum pages A core page can be dumped onto any free drum page
Processes Only the succession of various states has logical meaning for a process, not the execution speed Mutual synchronization enables cooperation between sequential processes Processor switches CPU among processes, temporarily delaying the progress of each current process The system is designed in terms of communicating sequential processes
Semaphores Semaphores are initialized with the value of 0 or 1 P-operation (down) decreases value of a semaphore by 1 If result is non-negative, process can continue If result is negative, process is stopped V-operation (up) increases value of a semaphore by 1 If result is positive, operation has no further effect If result is non-positive, a process on the waiting list is removed and made runnable Semaphores are used in two radically different ways in THE: for mutual exclusion or condition synchronization
Mutual Exclusion begin semaphore mutex; mutex := 1; parbegin begin L1: P(mutex); critical section 1; V(mutex); remainder of cycle 1; go to L1 end; begin L2: P(mutex); critical section 2; V(mutex); remainder of cycle 2; go to L2 end parend end Maximum value of mutex equals 1 Minimum value of mutex equals –(n-1) with n processes
Private Semaphores Each processes has a private semaphore initialized to 0 When progress depends on values of state variables: - P(mutex) “ inspect and modify state variables and perhaps V (private semaphore) ” - V(mutex) - P(private semaphore) When blocked processes need permission to continue: - P(mutex); “ modification and inspection of state variables including zero or more V operations on private semaphores of other processes ” - V(mutex)
Harmonious Cooperation The system is layered Sequential processes are cyclic - each process has a “ homing position ” (wait on private semaphore) - processes leave to accept a task and do not return until it is complete - a single initial task cannot generate an infinite number of tasks - processes only generate tasks for others at lower levels of the hierarchy Correctness concerns: - all processes should not be in their homing positions while there is still a pending unaccepted task - all processes eventually return to their homing position absence of “ circular waits ” -
System Hierarchy THE admits to a strict hierarchical structure Consists of 6 layers Level 5 - Operator Level 4 – User Programs Level 3 – Buffering I/O Level 2 – Message Interpreter Level 1 – Segment Controller Level 0 – Processor Allocation
Level 0 – Processor Allocation Scheduler software implements semaphores & processes Processes synchronize using semaphores Clock interrupts prevent monopoly of the CPU Priority-based scheduling Above this level, the actual processor has lost its identity - the CPU has been virtualized using processes
Level 1 – Segment Controller A sequential process synchronized with the drum interrupt and sequential processes of higher levels Responsible for memory storage and allocation Abstracts storage in terms of segments This layer virtualizes storage - above here, the actual storage pages have lost their identity
Level 2 – Message Interpreter Manages ‘ conversations ’ between operators and processes - only one conversation at a time - when a key is pressed, the character and an interrupt is sent to the machine - performs output commands needed for printing This layer virtualizes I/O - above here, each process thinks it has its own console - the console teleprinter has lost its identity
Level 3 – Buffering I/O Buffering of input streams Un-buffering of output streams Placed above level 2 to allow conversations with the operator (for error detection) Abstracts the actual peripherals - above here there are logical communication units
Levels 4 and 5 Level 4: independent-user programs Level 5: the operator (not created by us!) The EL X8 Operator's Console Image from http://www.science.uva.nl/museum/X1.html
Verification Performed layer-by-layer Level 0 tested before higher layers were added Level 1: all relevant states defined in terms of sequential processes working on core pages Layer-by-layer verification greatly reduced the number of relevant states needed for exhaustive testing Testing was able to continue even after the drum channel hardware failed
Conclusions New concepts Virtual CPU abstraction (process/thread) Semaphores for mutual exclusion Semaphores for condition synchronization Paged virtual memory Layered structure enabled thorough verification
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