ta9 Spring 2006 Amar Lior Adapted from Computer - PDF document

הנבמ םיבשחמ ta9 Spring 2006 Amar Lior Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3 rd edition 1 Control � Selecting the operations to perform (ALU, read/write, etc.) � Controlling the flow of data (multiplexor inputs) � Information comes from the 32 bits of the instruction � Example: add $8, $17, $18 Instruction Format: 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct � ALU's operation based on instruction type and function code Control � e.g., what should the ALU do with this instruction � Example: lw $1, 100($2) 35 2 1 100 op rs rt 16 bit offset � ALU control input 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR � Why is the code for subtract 0110 and not 0011? 1

Control � Must describe hardware to compute 4-bit ALU control input � given instruction type ALUOp 00 = lw, sw computed from instruction type 01 = beq, 10 = arithmetic � function code for arithmetic � Describe it using a truth table (can turn into gates): ALU Control bits Instruction ALU Instruction Funct Desired ALU opcode Op Operation field ALU Action control input LW 00 Load word XXXXXX Add 0010 SW 00 Store word XXXXXX Add 0010 Branch eq 01 Branch equal XXXXXX Subtract 0110 R-type 10 Add 100000 Add 0010 R-type 10 Subtract 100010 Subtract 0110 R-type 10 AND 100100 And 0000 R-type 10 OR 100101 Or 0001 R-type 10 Set less than 101010 Set on less 0111 then 5 Single Cycle Implementation Signal Effect when deasserted Effect when asserted Name RegDst The register destination number for the The register destination number comes from Write register comes from the rt field the rd field RegWrite None The register on the Write register input is written with the value on the Write data input ALUSrc The second ALU operand comes from the The second ALU operand is the sign extended second register file output lower 16 bits of the instruction PCSrc The PC is replaced by the output of the The PC is replaced by the output of the adder adder that computes the value of PC+4 that computes the branch target MemRead None Data memory content designated by the address input are put on the Read data output MemWrite None Data memory content designated by the address input are replaced by the value on the Write data input MemtoReg The value fed to the register Write data The value fed to the register Write data input input comes from the ALU comes from the data memory 6 2

0 M Add u x ALU 4 Add 1 result Shift left 2 RegDst Branch MemRead Instruction [31–26] MemtoReg Control ALUOp MemWrite ALUSrc RegWrite Instruction [25–21] Read Read register 1 PC address Read data 1 Instruction [20–16] Read Zero register 2 Instruction 0 ALU Read [31–0] Read ALU M 0 Address 1 Write result data u data 2 M Instruction Instruction [15–11] register M x u u memory 1 x x Write 0 1 data Registers Data Write memory data Instruction [15–0] 16 32 Sign ALU extend control Instruction [5–0] Memto- Reg Mem Mem Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0 R-format 1 0 0 1 0 0 0 1 0 lw 0 1 1 1 1 0 0 0 0 sw X 1 X 0 0 1 0 0 0 beq X 0 X 0 0 0 1 0 1 R-type Instruction 8 Multi Cycle PCWriteCond PCSource PCWrite Outputs ALUOp IorD ALUSrcB MemRead Control ALUSrcA MemWrite Op RegWrite MemtoReg [5–0] IRWrite 0 RegDst Jump M 1 u address Shift x 26 28 Instruction [25-0] [31–0] left 2 2 Instruction [31–26] PC [31–28] 0 PC 0 Instruction Read M Address [25–21] register 1 M u Read u x A Instruction data 1 x 1 Read Memory 1 Zero [20–16] register 2 0 MemData ALU ALU Instruction Registers ALUOut M Write result [15–0] Instruction u Read 0 x register B Write [15–11] data 2 Instruction 1 M data 4 1 register Write u 0 2 x data M Instruction 3 u [15–0] x 1 Memory 16 32 ALU data Sign Shift control register extend left 2 Instruction [5–0] 9 3

Action of the 1-bit control signals Signal Effect when deasserted Effect when asserted Name RegDest The register file destination Comes from rd number for the write register comes from rt RegWrite None Enable writing to the register file ALUSrcA The first ALU operand is the PC The first ALU operand comes from register A MemRead None Content of memory at the location specified by the Address input is put on Memory data output MemWrite None Memory content at the location specified by the Address input is replaced by value on Write data input MemtoReg The value fed to the register file The value fed to the register file Write data input comes from Write data input comes from the ALUOut MDR 10 Action of the 1-bit control signals Signal Effect when deasserted Effect when asserted Name IorD The PC is used to supply the ALUOut is used to supply the address to the memory unit address to the memory unit IRWrite None The output of the memory is written to the IR PCWrite None The PC is written the source is controlled by PCSource PCWriteCond None The PC is written if the Zero output from the ALU is also active 11 Actions of the 2-bit control signals Signal Value Effect Name (binary) ALUOp 00 The ALU perform an add 01 The ALU perform subtract 10 The funct field is used to determine the ALU operation ALUSrcB 00 Second input to ALU comes from B 01 Second input is the constant 4 10 Second input is the sign extended lower 16 bit of IR 11 Same as above but left shifted 2 b its (for branch) PCSource 00 Output of the ALU (PC+4) is sent to the PC for writing 01 The contents of the ALUOut are sent to the PC for writing 10 The jump target address (IR[25:0] shifted left 2 bits and concatenated with PC+4[31:28] is sent to the PC for writing 12 4

Simple Questions � How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label nop add $t5, $t2, $t3 sw $t5, 8($t3) Label: ... � What is going on during the 8th cycle of execution? � In what cycle does the actual addition of $t2 and $t3 take place? Delayed Branch � In a 5-stage pipeline we can make the control hazard a feature by redefining the branch � A delayed branch always executes the following instruction � Only the second instruction after the branch will be effected by the branch � Compilers and assemblers try to place an instruction that always execute after the branch � This place is called the delayed branch slots 14 Delayed Branch sub $t4, $t5, $t6 add $s1, $s2, $s3 … If $s1 = 0 then add $s1, $s2, $s3 .. ## Delay slot ## If $s2 = 0 then add $s1, $s2, $s3 … ## Delay slot ## If $s1 = 0 then … ## Delay slot ## sub $t4, $t5, $t6 … add $s1, $s2, $s3 .. If $s1 = 0 then If $s2 = 0 then add $s1, $s2, $s3 sub $t4, $t5, $t6 add $s1, $s2, $s3 If $s1 = 0 then sub $t4, $t5, $t6 15 5

Explanation to the examples � In (a) the delay slot is scheduled with an independent instruction from before the branch � In (b) the branch delay slot is scheduled from the target of the branch. This strategy is preferred when the branch is taken with high probability � In (c) the delay slot is scheduled from the not- taken fall-through � In order make (b) and (c) legal it must be OK to execute the sub instruction when branch goes in an unexpected direction. 16 Pros and Cons � Simple to implement � The compiler do the work, so if the compiler is improved there is no need to upgrade the hardware � Require more delay slots when the depth of the pipe is increased � There is a problem with binary compatability when taking code from a processor with X delay slots to a processor with Y delay slots (where X != Y) 17 Loop unrolling Loop: lw $t0, 0($s1) addu $t0, $t0, $s2 sw $t0, 0($s1) addi $s1, $s1, -4 bne $s1, $zero, Loop 18 6

Loop unrolling Loop: lw $t0, 0($s1) lw $t1, 4($s1) addu $t0, $t0, $s2 addu $t1, $t1, $s2 sw $t0, 0($s1) sw $t1, 4($s1) addi $s1, $s1, -8 bne $s1, $zero, Loop 19 7