הנבמ םיבשחמ ta8 Spring 200 6 Amar Lior Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3 rd edition 1
Exceptions and Interrupts � Exception: An unscheduled event that disrupts program execution and change its flow � Interrupts: An exception that comes from outside of the processor 2
Exception types: � Program � e.g. overflow, division by zero, using undefined instruction � Invoking the operating system from user program � systemcall � Timer � Generated by internal processor timer � Used in pre-emptive multi-tasking � I/O � from I/O controller (keyboard, disk) � Hardware failure � e.g. memory parity error 3
System call example .include "defines.h" .data hello: .string "hello world\n" .text .globl _start _start: movl $SYS_write,%eax // SYS_write = 4 movl $STDOUT,%ebx // fd = fileno(stdio) movl $hello,%ecx // buf = str movl $12,%edx // count = 0x6 int $0x80 movl $SYS_exit,%eax xorl %ebx,%ebx int $0x80 ret 4
Program Flow Control 5
How Exception are Handled � The address of the affected address is saved in the EPC register � The cause of the register is used to record the exception type. � Than the process jump to the exception address which is the operating system entry point for exception handling � In MIPS 0x8000 0180 � In SPIM 0x8000 0080 6
Interrupt Cycle � Added to instruction cycle � Processor checks for interrupt � Indicated by an interrupt signal � If no interrupt, fetch next instruction � If interrupt pending: � Suspend execution of current program � Save context � Set PC to start address of interrupt handler routine � Process interrupt � Restore context and continue interrupted program 7
Instruction Cycle (with Interrupts) - State Diagram 8
Multiple Interrupts � Disable interrupts � Processor will ignore further interrupts whilst processing one interrupt � Interrupts remain pending and are checked after first interrupt has been processed � Interrupts handled in sequence as they occur � Define priorities � Low priority interrupts can be interrupted by higher priority interrupts � When higher priority interrupt has been processed, processor returns to previous interrupt 9
Multiple Interrupts - Sequential 10
Multiple Interrupts - Nested 11
Example - PC Bus � 80x86 has one interrupt line � 8086 based systems use one 8259A interrupt controller � 8259A has 8 interrupt lines � Called Programmable Interrupt Controller PIC in short. 12
Sequence of Events � 8259A accepts interrupts � 8259A determines priority � 8259A signals 8086 (raises INTR line) � CPU Acknowledges � 8259A puts correct vector on data bus � CPU processes interrupt 13
PC Interrupt Layout 8259A 8086 IRQ0 System Timer IRQ1 Keyboard IRQ2 Slave 8259A IRQ3 INTR Serial port IRQ4 Serial port IRQ5 IDE controller IRQ6 Floppy controller IRQ7 LPT1 14
The 8086 Interrupt table � Fault – The return address point to the instruction that caused the exception � Trap – The return address points to the instruction after the one that caused the interrupt Number Description Type 0 Divide by zero Fault 1 Debug exception Trap or Fault 2 Trap Non-Maskable Interrupt (NMI) 3 Trap Breakpoint 4 Trap Overflow 6 Trap Invalid opcode 14 Fault Page Fault 32-255 Available for software and hardware interrupts 15
Exception Handling in MIPS (SPIM) � In MIPS processors, a part of the CPU called coprocessor 0 records the information that software needs to handle exception � Not all the coprocessor 0’s registers are implemented by SPIM � The mfc0 and mtc0 instructions are used to access those registers � The EPC contain the address of the offending instruction (if the exception was internal) � And the address if the next instruction if the exception was external 16
Interrupt related registers Register Register Usage Name Number BadVAddr 8 Memory address at which offending memory reference occurred Count 9 Timer Compare 11 Value compared against timer that caused interrupt when they match Status 12 Interrupt mask and enable bits Cause 13 Exception type and pending interrupt bits Epc 14 Address of instruction that caused exception 17
The Status Register � The interrupt mask contain a bit for each of the six hardware and two software interrupt level � Value of 1 means interrupt from that level can interrupt the processor � When an interrupt arrive it sets its “interrupt pending” bit in the cause register even if the mask is 0 � When an interrupt is pending it will interrupt the processor when the mask is enabled. � The user mode is 0 when in kernel mode and 1 when in user mode (always 1 in spim) � The exception level is usually 0 but is set to 1 when exception occur, in this situation interrupts are disabled and the EPC is not updated if another exception occur. Enable exception handler from being disturbed by an Exception or interrupt � If the interrupt enable bit is 1 interrupt are allowed e t n d p o i o u t e r l M l p r b e e r e a c t v e n x s e n I e E L U 15 8 1 0 4 18 Interrupt mask
Cause Register � The delayed branch is 1 if the last exception occurred in the delay slot of a branch � The interrupt pending bits become 1 when an interrupt is raised at a given hardware or software level � The exception code describe the cause of the exception through the codes in next slide 8 15 31 2 6 19 Exception Code Branch Delay Pending Interrupts
Exception codes Number Name Cause of Exception 0 Int Interrupt (hardware) 4 AdEL Address error exception (load or fetch) 5 AdES Address error exception (store) 6 IBE Buss error in instruction fetch 7 DBE Buss error on data load or store 8 Sys Syscall exception 9 Bp Breakpoint exception 10 RI Reserved instruction exception 11 CpU Coprocessor unimplemented 12 Ov Arithmetic overflow exception 13 Tr Trap 15 FPE Floating point exception 20
Handling the Exception � Exception and interrupts cause the MIPS processor to jump to a piece of code at address 0x8000 0180 (kernel address space) � Called the exception handler � This code examine the exception’s code and jumps to an appropriate point in the operating system � The operating system respond by terminating the process or by performing some action 21
Exception handler example 22
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