CS 35101 Computer Architecture Spring 2008 Chapter 3 Part 2 - PowerPoint PPT Presentation

CS 35101 Computer Architecture Spring 2008 Chapter 3 Part 2 (3.4-3.6, Apndx B) Taken from Mary Jane Irwin (www.cse.psu.edu/~mji) and Kevin Schaffer [ adapted from D. Patterson slides ] CS35101 Ch3.Part1 27 Steinfadt SP08 KSU

Head’s Up  Last week’s material  MIPS arithmetic - Reading assignment – 3.1-3.3  Exam 1 on 2/21 Thursday  This week’s material  MIPS arithmetic and ALU design - Reading assignment – 3.4-3.5, B.1-B.5 CS35101 Ch3.Part1 28 Steinfadt SP08 KSU

Overflow Detection  Overflow occurs when the result is too large to represent in the number of bits allocated  adding two positives yields a negative  or, adding two negatives gives a positive  or, subtract a negative from a positive gives a negative  or, subtract a positive from a negative gives a positive  On your own: Prove you can detect overflow by:  Carry into MSB xor Carry out of MSB 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 + 0 0 1 1 3 + 1 0 1 1 – 5 1 0 1 0 – 6 0 1 1 1 7 CS35101 Ch3.Part1 30 Steinfadt SP08 KSU

What operations does an ALU need to handle?  Adds:  Sub’s:  Multiply / Divide:  Logical Ops:  Branch / Comp’s: CS35101 Ch3.Part1 31 Steinfadt SP08 KSU

What operations does an ALU need to handle?  Adds: add, addi, addiu, addu  Sub’s: sub, subu  Multiply / Divide: mult, multu, div, divu  Logical Ops: and, andi, nor, or, ori, xor, xori  Branch / Comp’s: beq, bne, slt, slti, sltiu, sltu CS35101 Ch3.Part1 32 Steinfadt SP08 KSU

What operations does an ALU need to handle? Assume that the immediates are handled before they reach the ALU  Adds: add, addi, addiu, addu  Sub’s: sub, subu  Multiply / Divide: mult, multu, div, divu  Logical Ops: and, andi, nor, or, ori, xor, xori  Branch / Comp’s: beq, bne, slt, slti, sltiu, sltu CS35101 Ch3.Part1 33 Steinfadt SP08 KSU

What operations does an ALU need to handle? Assume that the immediates are handled before they reach the ALU  Adds: add, addu  Sub’s: sub, subu  Multiply / Divide: mult, multu, div, divu  Logical Ops: and, nor, or, xor  Branch / Comp’s: beq, bne, slt, sltu CS35101 Ch3.Part1 34 Steinfadt SP08 KSU

What operations does an ALU need to handle? Multiply and Divide will get their own hardware  Adds: add, addu  Sub’s: sub, subu  Multiply / Divide: mult, multu, div, divu  Logical Ops: and, nor, or, xor  Branch / Comp’s: beq, bne, slt, sltu CS35101 Ch3.Part1 35 Steinfadt SP08 KSU

What operations does an ALU need to handle? Check for Equality can be done with arithmetic functions (a=b if a-b = 0)  Adds: add, addu  Sub’s: sub, subu  Logical Ops: and, nor, or, xor  Branch / Comp’s: beq, bne, slt, sltu CS35101 Ch3.Part1 36 Steinfadt SP08 KSU

Building a 1-bit ALU What are the opcodes for the remaining functions that the ALU must support? 0 add 1 addu 2 sub What about the function codes? 3 subu What is the leading hex value 4 and for each Function Code? 5 or 6 xor 7 nor a slt b sltu CS35101 Ch3.Part1 37 Steinfadt SP08 KSU

MIPS Arithmetic and Logic Instructions 31 25 20 15 5 0 R-type: op Rs Rt Rd funct I-Type: op Rs Rt Immed 16 Type op funct Type op funct Type op funct ADDI 001000 xx ADD 000000 100000 000000 101000 ADDIU 001001 xx ADDU 000000 100001 000000 101001 SLTI 001010 xx SUB 000000 100010 SLT 000000 101010 SLTIU 001011 xx SUBU 000000 100011 SLTU 000000 101011 ANDI 001100 xx AND 000000 100100 000000 101100 ORI 001101 xx OR 000000 100101 XORI 001110 xx XOR 000000 100110 LUI 001111 xx NOR 000000 100111 CS35101 Ch3.Part1 38 Steinfadt SP08 KSU

Design Trick: Divide & Conquer  Example: assume the immediates have been taken care of before the ALU  now down to 10 operations 0 add  can encode in 4 bits 1 addu 2 sub  Break the problem into simpler 3 subu problems, solve them and glue 4 and together the solution 5 or 6 xor 7 nor Next up: Section B, The Basics of Logic Design a slt b sltu CS35101 Ch3.Part1 39 Steinfadt SP08 KSU

Combinational vs. Sequential  Combinational logic has no memory, outputs depend entirely on inputs  Sequential logic has memory, outputs depend on both inputs and the current contents of memory  Memory in sequential logic is called state CS35101 Ch3.Part1 40 Steinfadt SP08 KSU

Combinational Logic  Truth tables  Logic equations  Gates CS35101 Ch3.Part1 41 Steinfadt SP08 KSU

Truth Tables  Gives values of outputs for each combination of inputs Inputs Outputs  Logic block with n A B C D inputs is defined by a truth table with 2 n 0 0 0 0 entries 0 1 0 1 1 0 0 1 1 1 1 1 CS35101 Ch3.Part1 42 Steinfadt SP08 KSU

Logic Equations  OR (Logical sum): A + B  AND (Logical product): A · B  NOT (Logical complement): A ' CS35101 Ch3.Part1 43 Steinfadt SP08 KSU

Boolean Algebra  Identity laws  A + 0 = A  A · 1 = A  Zero and One laws  A + 1 = 1  A · 0 = 0  Inverse laws  A + A ' = 1  A · A ' = 0 CS35101 Ch3.Part1 44 Steinfadt SP08 KSU

Boolean Algebra (cont'd)  Commutative laws  A + B = B + A  A · B = B · A  Associative laws  A + ( B + C ) = ( A + B ) + C  A · ( B · C ) = ( A · B ) · C  Distributive laws  A · ( B + C ) = ( A · B ) + ( A · C )  A + ( B · C ) = ( A + B ) · ( A + C ) CS35101 Ch3.Part1 45 Steinfadt SP08 KSU

Gates  AND gate  OR gate  Inverter (NOT gate) CS35101 Ch3.Part1 46 Steinfadt SP08 KSU

Inversion Bubbles  Inverters are so commonly used that designers have developed a shorthand notation  Instead of using explicit inverters, you can attach bubbles to the inputs or outputs of other gates CS35101 Ch3.Part1 47 Steinfadt SP08 KSU

Universal Gates  Any combinational function can be built from AND, OR and NOT gates  However, there are universal gates that alone can implement any function  NAND and NOR are two such gates  NAND and NOR are AND and OR gates with inverted outputs CS35101 Ch3.Part1 48 Steinfadt SP08 KSU

Decoder  A decoder asserts exactly one of its 2 n outputs for each combination of its n inputs  The n inputs are interpreted as an n -bit binary number CS35101 Ch3.Part1 49 Steinfadt SP08 KSU

Decoder (cont'd) Inputs Outputs In2 In1 In0 Out7 Out6 Out5 Out4 Out3 Out2 Out1 Out0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 CS35101 Ch3.Part1 50 Steinfadt SP08 KSU

Multiplexor  A multiplexor selects one of its 2 n data inputs, based on the value of its n selector inputs, to become its output  The n selector inputs are interpreted as an n -bit binary number CS35101 Ch3.Part1 51 Steinfadt SP08 KSU

Arrays of Logic Elements CS35101 Ch3.Part1 52 Steinfadt SP08 KSU

Two-Level Logic  Any combinational function can be expressed in a canonical two-level representation  Sum of products is a logical sum (OR) of logical products (AND)  Product of sums is just the opposite CS35101 Ch3.Part1 53 Steinfadt SP08 KSU

Sum of Products CS35101 Ch3.Part1 54 Steinfadt SP08 KSU

Full Adder CarryIn a CIN A B COUT SUM Sum 0 0 0 0 0 0 0 1 0 1 b 0 1 0 0 1 0 1 1 1 0 CarryOut 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 CS35101 Ch3.Part1 55 Steinfadt SP08 KSU

Subtraction  Subtraction is implemented by negating the second operand before addition  To negate a number in two's complement, invert the bits and add one  a – b = a + -b = a + (~b + 1) = a + ~b + 1  We can take advantage of the carry in to the LSB in order to add one to result CS35101 Ch3.Part1 56 Steinfadt SP08 KSU

Adder/Subtractor CS35101 Ch3.Part1 57 Steinfadt SP08 KSU

Delay in Ripple Carry Adders  Ripple carry adders are simple, but slow  The critical path (longest path any signal takes) goes through all the full adders  Therefore the delay is O ( k ) for a k -bit adder  Design trick – throw hardware at it (Carry Lookahead [info located in Appendix B.6]) CS35101 Ch3.Part1 58 Steinfadt SP08 KSU

Clocks  A clock is a logic signal that oscillates between 0 and 1 with a fixed frequency  When the clock transitions from 0 to 1, this is called a rising (or positive) edge ; a transition from 1 to 0 is a falling (or negative) edge  Logic can be built to respond to the value of the clock ( level-sensitive ) or to its edges ( edge- sensitive ) CS35101 Ch3.Part1 59 Steinfadt SP08 KSU

Clocks  C lock period (or clock cycle time ) is the inverse of the clock frequency  Example: a clock with a period of 500 ps has a frequency of 2 GHz CS35101 Ch3.Part1 60 Steinfadt SP08 KSU

Latches  Latches are level-sensitive storage elements  The simplest type of latch is the S-R latch (set-reset latch)  Q is the currently stored value CS35101 Ch3.Part1 61 Steinfadt SP08 KSU

Clocked Latches  A D latch (data latch) is an example of a clocked latch  When the clock (C) is high, the data input (D) is copied to the output  When the clock is low, the output remains unchanged CS35101 Ch3.Part1 62 Steinfadt SP08 KSU