System-on-Chip Design Data Flow hardware Implementa8on Hao Zheng - PowerPoint PPT Presentation

System-on-Chip Design Data Flow hardware Implementa8on Hao Zheng Dept. Comp Sci & Eng U of South Florida haozheng@usf.edu (813) 9744757 1

Single-Rate SDF to Hardware • Single-rate SDF: all producJon/consumpJon rates are a fixed number = 1. – The enJre circuit controlled by a single clock. • ImplementaJon – Actors -> combinaJon circuits – Queues -> wires – IniJal tokens -> registers. 2

Single-Rate SDF to Hardware initial token value = a sort out1 = (a > b) ? a : b; out2 = (a > b) ? b : a; 1 1 1 1 sort diff diff out1 = (a !=b) ? a – b : a; 1 1 1 1 out2 = b; initial token value = b Fig. 3.10 Euclid’s greatest common divisor as an SDF graph 3

Single-Rate SDF to Hardware SORT DIFF compare compare SORT DIFF 1 0 sub 0 1 REGISTER Fig. 3.11 Hardware implementation of euclid’s algorithm Can lead to long combinaJon paths. 4

SDF HW Implementa8on • CombinaJonal path is a sequence of actors s.t. edges between these actors do not have iniJal token. • CriJcal path is a combinaJonal path s.t. the sum of latencies of all actors on that path is the longest. • CriJcal path delay determines the clock frequency. – Should be minimized to increase clock speed. 5

Pipelining: Break Long Comb. Paths Fig. 3.12 SDF graph of a x1 x0 x2 simple moving-average in c2 c1 c0 application + + out = x 0 · c 2 + x 1 · c 1 + x 2 · c 0 out 6

Pipelining: Break Long Comb. Paths Fig. 3.13 Pipelining the x2 x1 x3 moving-average filter by in c2 c1 inserting additional tokens (1) c0 c0x2 c1x1 + c2x0 + out = x 0 · c 2 + x 1 · c 1 + x 2 · c 0 out 7

Pipelining: Break Long Comb. Paths Fig. 3.14 Pipelining the x3 x2 x4 moving-average filter by in c2 c1 c0 inserting additional tokens (2) c0x3 c1x2 c2x1 + c2x0 C0x2+c1x1 + out = x 0 · c 2 + x 1 · c 1 + x 2 · c 0 out 8

Pipelining: Break Long Comb. Paths in x3 x2 x4 in c2 c1 c0 c0 c1 c2 c0x3 c1x2 c2x1 + c2x0 C0x2+c1x1 + + + out out 9

Pipelining: PiCall != ADD ADD IN IN double-accumulator accumulator for odd/even samples Do Not add iniJal tokens unless they can be injected by a sequence of actor firings. 10

Mul8-Rate Expansion (Sec. 2.5.1) 1 1 3 2 1 1 OUT IN A B PASS 2 2 3 3 Firing Rate a This single-rate DFG OUT0 IN0 A0 B0 b can be mapped to c HW as shown previously. OUT1 B1 d e OUT2 B2 IN1 A1 f 11

HW/SW Hybrid Implementa8on 1 1 ctr snk Hardware 8051 Design Microcontroller P0 data ctr P1 snk req FIFO Interface btw. Interface btw. P2 SW & CPU HW & CPU ack 12

Reading Guide • SecJon 3.2 - 3.3, the CoDesign book. 13