MP System-on-Chip: MP System-on-Chip: Embedded Test, Diagnosis and - PowerPoint PPT Presentation

MP System-on-Chip: MP System-on-Chip: Embedded Test, Diagnosis and Embedded Test, Diagnosis and Repair in Practice Repair in Practice Yervant Zorian Virage Logic Corp zorian@viragelogic.com

Contents Contents � Introduction � SoC yield & reliability challenges � Optimization loop concept � Infrastructure IP & resource partitioning � Examples of embedding infrastructure IP � Conclusions

Introduction Introduction � Cost � reduce semiconductor fabrication cost by improving manufacturing yield � Time-to-Volume � Short time to market and short product lifecycle � faster yield optimization impacts market entry time and bottom line � Quality � Production of high quality manufactured silicon

Deep Submicron Trends Deep Submicron Trends � Number of transistors � Mixed technologies � Shrinking geometries � Process layers � New process material � High performance

Deep Submicron Impact Deep Submicron Impact � Miniaturization and High Performance result in � Finer and denser semiconductor fabrication � Increased susceptiblity � Increased defectivity � Lower manufacturing yield and reliability � Observed as � Defect density � Realistic Faults � Timing problems � Transient or Soft Errors

IC Realization Flow IC Realization Flow IP Design IP Design IP Design Characterization Characterization Characterization SoC Design SoC Design SoC Design Production Production Production Ramp Up Ramp Up Ramp Up Volume Volume Volume Fabrication Fabrication Fabrication Test Test Test Failure Failure Failure Assembly Assembly Assembly Analysis Analysis Analysis Packaging Packaging Packaging In- -Field Field In In-Field

Yield Life Cycle Curve Yield Life Cycle Curve 100 Yield Assessment (%) 90 Fab Yield 80 Optimization 70 60 Yield 50 Learning Curve 40 30 20 10 0 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 Design Production Ramp Up Volume

Yield Life Cycle Curve Yield Life Cycle Curve 100 Yield Assessment (%) New Yield 90 Learning Fab Yield 80 Curve Optimization 70 Design Yield 60 Optimization Yield 50 Learning Curve 40 30 20 10 0 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 Design Production Ramp Up Volume

Yield Life Cycle Curve Yield Life Cycle Curve 100 Yield Assessment (%) New Yield 90 Learning Fab Yield 80 Curve Optimization 70 Design Yield 60 Optimization Yield 50 Learning Curve 40 30 20 10 0 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 Design Production Ramp Up Volume

Yield Life Cycle Curve Yield Life Cycle Curve 100 Yield Assessment (%) New Yield 90 Learning Fab Yield 80 Curve Optimization 70 Design Yield 60 Optimization Yield 50 Learning Curve 40 30 20 10 0 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 Design Production Ramp Up Volume

Yield Life Cycle Curve Yield Life Cycle Curve 100 Yield Assessment (%) New Yield 90 Learning Fab Yield 80 Curve Optimization 70 Design Yield 60 Optimization Yield 50 Learning Curve 40 30 20 10 0 10 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 Design Production Ramp Up Volume

1. Yield Learning Challenge 1. Yield Learning Challenge � Semiconductor process evolving and introducing new material and techniques � result in new generation of yield limiting factors � Small geometries � result in devices more susceptible to systematic and random defects and higher defect densities per layer � Increased time-to-market pressure � result in chip volume production at lower yield level � Disaggregated semiconductor industry � result in F-IP providers assuming yield optimization responsibility � Need process monitor IP and yield prediction and optimization for each new design (IP and SoC)

2. Embedded Memory Challenge 2. Embedded Memory Challenge

2. Embedded Memory Challenge 2. Embedded Memory Challenge 2 Mb 4 Mb 8 Mb 1 Mb 16 Mb 24 Mb 32 Mb 100 90 80 70 ) ld (% 60 ie Memory yield (without redundancy) Y 50 Memory Yield with redundancy ory m 40 Width of die in mm 12.00 e M 30 Height of die in mm 12.00 Defect density for logic 20 in # per sq. in. 0.4 Defect density for memory 10 in # per sq. in. 0.8 0 Process technology 0.13 um 5 3 11 22 86 43 65 3 5 11 22 43 65 86 2.69 5.39 10.78 21.56 43.11 64.67 86.22 % Memory on die Percent of Memory on die

3. Failure Analysis Challenge 3. Failure Analysis Challenge � Traditional physical failure analysis steps - � Fault localization � Silicon de-processing � Physical characterization and inspection � Small geometries result in – � Finding smaller more subtle defects � Tighter pitches require greater spatial resolution � Backside analysis due to metal layers & flip-chip � Need to gather failure data using diagnosis IP and analyze obtained data by off-chip fault localization methodologies and tools

4. High Performance Challenge 4. High Performance Challenge � Increased performance require increased accuracy for proper resolution of timing signals � Semiconductor off-chip speed improved 30% per year, test accuracy improved 12% per year � Tester timing errors approaching cycle time of faster device � Yield loss due to tester inaccuracy (extra guard- bending performed at test stage) � Need for measuring and analyzing time specifications using embedded timing probes with high accuracy

5. Transient Error Challenge 5. Transient Error Challenge � Smaller geometries and reduced power supplies result in reduced noise margins � Soft errors,timing faults, crosstalk are major signal integrity problems � SoC needs self correcting, i.e. embedded robustness, engine in order to resist to this challenge

Yield Optimization Loops Yield Optimization Loops � Need for Advance yield optimization solutions � Introduced at different stages of chip realization flow � Yield optimization feedback loops – comprised of three steps � Detection, Analysis, Correction � Three step loops either reside completely off-chip, partially on-chip/off-chip or embedded on-chip � Examples of yield optimization feedback loops

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization SoC Design SoC Design SoC Design Production Production Production Ramp Up Ramp Up Ramp Up Volume Volume Volume Fabrication Fabrication Fabrication Test Test Test Failure Failure Failure Assembly Assembly Assembly Analysis Analysis Analysis Packaging Packaging Packaging In- -Field Field In In-Field

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization SoC Design SoC Design SoC Design - Detection D Production Production Production Ramp Up Ramp Up Ramp Up - Analysis A Volume Volume Volume - Correction C Fabrication Fabrication Fabrication Test Test Test Failure Failure Failure Assembly Assembly Assembly Analysis Analysis Analysis Packaging Packaging Packaging In- -Field Field In In-Field

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization C D A 1 SoC Design SoC Design SoC Design - Detection D Production Production Production Ramp Up Ramp Up Ramp Up - Analysis A Volume Volume Volume - Correction C Fabrication Fabrication Fabrication Test Test Test Failure Failure Failure Assembly Assembly Assembly Analysis Analysis Analysis Packaging Packaging Packaging In- -Field Field In In-Field

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization C D A 1 SoC Design SoC Design SoC Design C - Detection A 2 D Production Production Production Ramp Up Ramp Up Ramp Up D - Analysis A Volume Volume Volume - Correction C Fabrication Fabrication Fabrication Test Test Test Failure Failure Failure Assembly Assembly Assembly Analysis Analysis Analysis Packaging Packaging Packaging In- -Field Field In In-Field

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization C D A 1 SoC Design SoC Design SoC Design C - Detection A 2 D Production Production Production Ramp Up Ramp Up Ramp Up D - Analysis A Volume Volume Volume - Correction C Fabrication Fabrication Fabrication D Test Test Test Failure Failure Failure 3 Assembly Assembly Assembly A Analysis Analysis Analysis Packaging Packaging Packaging C In- -Field Field In In-Field

Yield Optimization Loops Yield Optimization Loops IP Design IP Design IP Design Characterization Characterization Characterization C D A 1 SoC Design SoC Design SoC Design C - Detection A 2 D Production Production Production Ramp Up Ramp Up Ramp Up D - Analysis A Volume Volume Volume - Correction C Fabrication Fabrication Fabrication D D Test Test Test Failure Failure Failure 3 Assembly Assembly Assembly A A Analysis Analysis Analysis 4 Packaging Packaging Packaging C C In- -Field Field In In-Field