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High-Performance Embedded High-Performance Embedded Systems-on-a-Chip Systems-on-a-Chip Sanjay Rajopadhye Sanjay Rajopadhye Computer Science, Colorado State Computer Science, Colorado State University University Lecture 3: Systolic Arrays

High-Performance Embedded High-Performance Embedded Systems-on-a-Chip Systems-on-a-Chip Sanjay Rajopadhye Sanjay Rajopadhye Computer Science, Colorado State Computer Science, Colorado State University University Lecture 3: Systolic Arrays & Systolic Lecture 3: Systolic Arrays & Systolic Synthesis Synthesis
2 Systolic Synthesis With mathematical specification (SARE + reductions), do the following (not necessarily in order): 1. Serialize reductions and Align inputs and outputs 2. Localize dependences 3. Schedule the SARE 4. Allocate the computation to processors 5. Transform the SARE 6. Generate the HDL
3 Example: Convolution Initial specification: n − 1 � w j ∗ x i − j y i = j =0
4 Serialization & Alignment Replace (unbounded fan-in) � by sequence of binary additions. Align input and output vars. �� yi = Y [ i, n − 1] �� j = 0 : wj ∗ xi − j �� Y [ i, j ] = j > 0 : Y [ i, j − 1]+ �� wj ∗ xi − j ��
5 Localization/Uniformization Remove unbounded fan-out (i.e., “long”) dependences. yi = Y [ i, n − 1] �� j = 0 : W [ i, j ] ∗ X [ i, j ] �� Y [ i, j ] = j > 0 : Y [ i, j − 1]+ �� W [ i, j ] ∗ X [ i, j ] � �� j = 0 : xi �� X [ i, j ] = j > 0 : X [ i − 1 , j − 1] �� i = 0 : wj �� W [ i, j ] = �� i > 0 : W [ i − 1 , j ] ��
6 Scheduling & Allocation ��

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