Embedded Quality for Test Embedded Quality for Test Yervant Zorian - PowerPoint PPT Presentation

Embedded Quality for Test Embedded Quality for Test Yervant Zorian Yervant Zorian LogicVision, Inc. LogicVision, Inc.

Electronics I ndustry Electronics I ndustry I Achieved Successful Achieved Successful I Penetration in Diverse Penetration in Diverse Domains Domains

Electronics I ndustry ( cont cont) ) Electronics I ndustry ( I Met User Met User Quality Quality Requirements Requirements I – satisfying users’ to buy products satisfying users’ to buy products again again – Created an Unprecedented Dependency - market-driven product Competitors U s e r s Electronic Product

Quality Requirements at Chip Level Quality Requirements at Chip Level I Manufacturing Test for Chips Manufacturing Test for Chips I I To achieve board defect levels < 1% To achieve board defect levels < 1% I To maintain ATE cost To maintain ATE cost I Diagnostics for Chip Manufacturing Diagnostics for Chip Manufacturing I I To enable physical failure analysis To enable physical failure analysis I To enhance yield by enabling repair for large memories To enhance yield by enabling repair for large memories

Quality Requirements at Board Level Quality Requirements at Board Level I Board Level Manufacturing Test Board Level Manufacturing Test I I Full Coverage of board level defects Full Coverage of board level defects I Chip failures (handling, stress, infant mortality) Chip failures (handling, stress, infant mortality) I Diagnostics for Board Level Manufacturing Diagnostics for Board Level Manufacturing I I To determine failed interconnect or chip To determine failed interconnect or chip I To enable speedy repair To enable speedy repair

Conventional Test Flow Conventional Test Flow I Functional Patterns Functional Patterns I I Deterministic ATPG Deterministic ATPG I with Scan Path with Scan Path I Full Pin Count Full Pin Count I Automatic Test Automatic Test Equipment Equipment

Emerging Electronics I ndustry Emerging Electronics I ndustry I Products Shift to Communications and Connectivity Products Shift to Communications and Connectivity I I Maintain competitive edge by providing: Maintain competitive edge by providing: I – Greater Product Greater Product Functionality Functionality – – Lower Lower Cost Cost (product life cycle) (product life cycle) – – Reduced Reduced Time-to-Profitability Time-to-Profitability – – Higher Quality and Higher Quality and Reliability Reliability –

Emerging I nfrastructure Emerging I nfrastructure “The internet runs on silicon.” “The internet runs on silicon.” Andy Grove Andy Grove “The information superhighway “The information superhighway is paved in silicon.” is paved in silicon.” Scott McNealey Scott McNealey

Emerging I ndustry Trends Emerging I ndustry Trends I Caused new technologies: Caused new technologies: I Greater Complexity Greater Complexity Increased Performance Performance Increased Higher Density Density Higher Lower Power Power Dissipation Dissipation Lower

The Key Challenge The Key Challenge I To meet Users’ Quality Requirements for To meet Users’ Quality Requirements for I new Technologies new Technologies I To assure New Products are adequately: To assure New Products are adequately: I Debugged, Tested, Verified, Measured, Repaired, ...

Emerging New Challenges Emerging New Challenges I Observe Implications on Product Realization Observe Implications on Product Realization I I Analyze Existing Quality Assurance Approaches Analyze Existing Quality Assurance Approaches I I Identify Challenges Identify Challenges I I Demonstrate Potential Solutions Demonstrate Potential Solutions I Design Manufacturing Diag. & Yield Field Service

Design Challenge: Quality Design Challenge: Quality Implications of SIA Roadmap: Testing I Implication: Implication: I Testing Complexity Index - [#Tr. per Pin] 1.60E+ 5 – # of Transistors per pin # of Transistors per pin – 1.40E+ 5 (Testing Complexity (Testing Complexity 1.00E+ 5 8.00E+ 5 Index) Index) 6.00E+ 4 4.00E+ 4 2.00E+ 4 – increased internal speed increased internal speed 0.00E+ 0 vs external vs external Year 1992 1995 1998 2001 2004 2007 F. Size [ µ m] 0.5 0.35 0.25 018 0.12 0.1 Source: W. Maly, 1996 Source: SIA Roadmap Design Manufacturing Diag. & Yield Field Service

Design Challenge: Quality Design Challenge: Quality I Leverage Internal Bandwidth Leverage Internal Bandwidth vs vs External External I Bandwidth Bandwidth System-on-Chip I/O Drivers I/O Drivers off-chip bus on-chip bus ASIC DRAM ASIC DRAM 32-bits 128/512-bits

Design Challenge: Quality Design Challenge: Quality I External Bandwidth External Bandwidth I – max bits of data/time max bits of data/time – 250 from ATE to IC from ATE to IC 200 Internal Bdw. I Internal Bandwidth Internal Bandwidth I 150 (Capacity*IntFreq Bandwidth max bits of data/time from on- max bits of data/time from on- External Bdw 100 Gap (IO*ExtFreq) chip test resource to chip test resource to 50 embedded core embedded core 0 Y 1 9 9 5 Y1998 Y 2 0 0 1 Y 2 0 0 4 Y2007 Y2010 Bandwidth Gap I Bandwidth Gap I

Design Challenge: Quality Design Challenge: Quality I External Test Data Volume External Test Data Volume I Memory can be extremely high can be extremely high External Test (function of chip (function of chip Super Tester complexity) Logic complexity) Pattern Generation . Precision Timing I Requires deep tester Requires deep tester I Diagnostics Power Management Mixed- Test Control memory for scan I/O pins memory for scan I/O pins Signal Very high pin count I Slow test throughput with Slow test throughput with Deep memory I Slow throughput I/Os & long scan chains, especially long scan chains, especially Interconnects for core-based designs for core-based designs

Design Challenge: Quality Design Challenge: Quality I Solution: Dedicated Built-In Solution: Dedicated Built-In I Memory H/W for embedded test H/W for embedded test Embedded functions functions Test (Built-in) External Logic Test Repartition tester into I Repartition tester into I Pattern Generation . Result Compression Standard Precision Timing embedded test and embedded test and Digital Diagnostics Mixed- Tester Power Management Signal external test functions external test functions Test Control Limited Speed/ Support for Accuracy Board-level Test I/Os & I Include low H/W cost Include low H/W cost I System-Level Test Interconnects Low Cost-per-Pin and high data volume and high data volume Chip, Board or System embedded-quality for test embedded-quality for test Source: LogicVision

Design Challenge: Quality Design Challenge: Quality Source/ Sink Source/ Sink Scan Paths Test Access External Test Embedded Test External Test Source/ Source/ Source/ High- Sink Sink Bandwidth Sink Low - High bandwidth bandwidth External Test Embedded Test External Test Embedded Test

Design Challenge: TTM Design Challenge: TTM Implication: Emergence I Implication: Emergence I of reusable core-based of reusable core-based design design I Multiple hardware Multiple hardware I description levels description levels (hard, soft, firm) (hard, soft, firm) I Standard IC functions Standard IC functions I (library elements) and (library elements) and Source: VSI Alliance legacy cores legacy cores

SOC Market Growth SOC Market Growth Worldwide Revenue (Billions of Dollars) 30 25 20 15 10 5 0 1998 1999 2000 2001 2002 2003 Source: Dataquest

Paradigm Shift in SOC Design Paradigm Shift in SOC Design System on a Chip System on a board

Design Challenge: TTM Design Challenge: TTM I SOC manufactured and SOC manufactured and I tested in single stage tested in single stage System-on-Board (SOB) System-on-Chip (SOC) Process Process I Core I/Os often more than Core I/Os often more than I Core Design UDL Design IC Design ASIC Design Chip I/Os Chip I/Os IC Manuf . ASIC Manuf. I Test generation difficult due Test generation difficult due I ASIC Test IC Test to limited core design to limited core design SOC Integration SOB Design knowledge knowledge SOC Manuf. SOB Manuf. I Direct access to core ports Direct access to core ports I SOB Test SOC Test unavailable unavailable I Core & UDL test part of Core & UDL test part of I System-On-Chip test System-On-Chip test

Design Challenge: TTM Design Challenge: TTM I Built-in dedicated H/W to Built-in dedicated H/W to I create create autonomous autonomous internal core test internal core test I Built-in dedicate System- Built-in dedicate System- I On-Chip test optimization On-Chip test optimization I Built-In Built-In standard standard core test core test interface for each core interface for each core