Status of the Pixel Vertex Detector (PXD) Reminder: DEPFET Module Production Steps Status of ASICs SMD Assembly Pilot Production Services, DAQ, Slow Control CO2 Cooling Mechanics PXD Milestones & Schedule C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 1
Remnder: DEPFET Technology SWG SWG gate DEPFET- matrix reset Depleted p-channel FET off off reset on off off n x m pixel off off clear gate I DRAIN V V GATE, ON CLEAR, ON V V CLEAR, OFF drain GATE, OFF DCDpl V CLEAR-Control DHPT 0 suppression DAQ output ASICs: Charge collected in internal gate Turn on FET SW (Switcher) Digitize FET (drain) current DCD (drain current digitizer) Clear internal gate DHP (data handling processor) Turn off FET C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9-11, 2015, Plenary 2
Production Steps of PXD Ladders DEPFET Production sensor wafer sensor wafer SOI process handle wafer handle wafer (after 1. implant backside 1. implant backside 2. bond sensor wafer 2. bond sensor wafer 3. thin sensor side 3. thin sensor side 4. process DEPFETs 4. process DEPFETs 5. structure resist, 5. structure resist, on sensor wafer on sensor wafer to handle wafer to handle wafer to desired thickness to desired thickness on top side on top side etch backside up etch backside up 2 Al) to oxide/implant to oxide/implant 4 types of Kapton 4 types of modules C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 3
Phases of DEPFET Sensor Production metal_2 metal_2 oxide oxide polySi_2 polySi_1 metal_1 polySi_2 polySi_1 metal_1 p+ n+ p+ n+ deep n deep n deep p deep p n bulk n bulk Phase I – before metal Phase II ‐ Alu Phase III – thinning and Cu • • • Implantations Metal 1 Handle wafer removal • • • Polysilicon isolation Dielectric deposition • • • Dielectric depositions Metal 2 Metal 3 • Passivation Completed Pilot Run (10% of wafers) ‐ Most critical step: Phase II, developed using “EMCM” (= Sensor ¬ DEPFET) ‐ Challenges: long and narrow metal lines, choose optimal dielectric between M1/M2, ensure good contact M1 ‐ >M2 and M2 ‐ >M3, complicated topography C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 4
Status of ASICs 2 nd generation ASICs Switcher - used in EMCM electrical tests (Gated) DEPFET - used for the pilot run Sensor 3 rd generation under design: - ASIC-Review in July, (+Report) - Improve communication between DCD-DHPT - Faster Switcher DCD Final Submission: (pipe SWG, DSPT : August DCD: : September ‐ line) Final ASICs back in January 2016, to be installed for DESY test and BEAST 2 DHP (1.0) C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 5
SMD Production Technology • SMD was under development with two options: (IFIC & HLL) • prototypes of transport and process jigs available • @IFIC/NTC: solder ball jetting – process on new machine being installed at NTC, but problem still with Cu oxide layer • @HLL: solder paste dispensing: method has been proven to work successfully @HLL @IFIC/NTC (PacTech) Decision: @HLL C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 6
Status of the Pilot Run Production Highlight (see photo): First COMPLETE DEPFET module from PXD9 pilot production: Sensor, ASICs and SMDs (Kapton cable ready for soldering), tests will start in September, finish by Nov. 2015) Pilot Production: 3/30 “hot” wafers (W30, W35, W36) still a lot of process control, tests, measurements “on the fly” [each wafer has 6 sensors (4 Layer2, 2 Layer1), PXD: 24 L2, 16 L1 ] Status : ‐ W30 finished up to Kapton assembly ( ‐ > Sep. 14) ‐ W36 Cu process repeated, W35 ready for thinning Main production (Phase 2/3) will start in Dec. 2015 (for 6 months) C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 7
Status of Kapton Cables 4 types: layer 1 (I_Fwd, I_Bwd), layer 2 (O_Fwd, O_Bwd) First samples (15) “O_Bwd” delivered Design “O_Fwd” finished in July, design of I_BWD ongoing 4 th cable (I_FWD) to be delivered by spring 2016 Design MPI, production by Taiyo (Japan) C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 8
Test Setup for Kapton Cable Solder + Wire Bonding (not removable) 2 Samtec Connectors (removable) Measurement Adapter Adapter L2bwd Kapton Device Bond Area Patch Panel Performance of Kapton OK (as specified) The 2 Samtec connectors are missing on this picture! C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 9
PXD Production Steps and Locations Item Where DEPFET Sensor (Phases I, II and III) Semiconductor Lab (HLL) Flip chipping of ASICs IZM Berlin mount SMDs (classify, no immediate rework) HLL Add Kapton cable, wire bonding MPI Munich Gluing of two modules (= „ladder“) MPI / HLL Assembly of PXD half shells MPI Munich Commissioning PXD MPI Munich Assembly of PXD and Beam pipe KEK clean room (B1) Completion of assembly with SVD (= „VXD“) KEK clean room (B1) Commissioning of VXD KEK clean room (B1) Installation of VXD into Belle II on SuperKEKB beam line C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 10
Services & DAQ Application specific PS unit successfully used in the EMCM module tests. Production of 50 units is under way (includes spares). Kapton prototype(L2BWD) for Pilot run successfully tested, including bending. Pocket-Onsen system installed at KEK, tested successfully with HLT and EVB Next steps: 30 kHz high rate test in 10/2015, DESY test 04/2016: Here support needed (again) by KEK DAQ group Optical transmission (dock->DHH) tested for radiation hardness: Glenair OK, now serious steps towards realization Stefan Rummel 11 C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 11
Injection “Noise”: PXD Gating Junk charge Laboratory test with ASICs at full speed not stored “Continuous” injection ( Δ I/I very small) Good progress, tuning continues C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 12
Injection “Noise”: PXD Gating Signal charge not destroyed To be discussed: GM can be run with or without readout Pro : no loss of data Con (?) : out of sync with machine revolution time C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 13
Slow Control & Cooling PS / DHE / JTAG control and startup sequences stable and in daily use, including software interlock. IPMI interface for ONSEN with actual hardware successfully tested. IBBelle CO 2 cooling plant GUI in development for commissioning @ MPI First GUI demonstrator according to new guidelines under development. Milestone: Full system test during next test beam @ DESY (April 2016) CO2 Cooling unit (“IBBelle”) for VXD under construction at MPI (on schedule). TÜV being involved in certification process. A first meeting scheduled for Sep. 30 at MPI Stefan Rummel 14 C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 14
IBBelle Construction @ MPI Built in two phases ( due to space limitations in Tsukuba hall): 1. “Little Brother”: fully functioning CO2 unit, but no operation redundancy 2. Later: add “Little Sister”, identical, but no accumulator Stefan Rummel C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 15
IBBelle Construction @ MPI Construction on schedule, industrial chiller to be delivered end of September Stefan Rummel C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 16
Cooling “Strategies” CO2 cooling needed in the following phases: - assembly of “DESY Test” ladders at MPI MPI cooler (alcohol, OK for SCB) - DESY Test itself MARCO (needs new pump) - Assembly of half shells @ MPI MPI Cooler - BEAST Phase 2 @ KEK (in Belle) IBBelle (or MARCO) - Test of VXD @ KEK B1 MARCO (or IBBelle) TÜV certification for MARCO also needed (will be addressed in the pre-meeting with TÜV on Sep. 30, 2015) C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 17
[PXD] Mechanics Present activities: - Preparation of jigs for the module / ladder production - Final design and construction for AIM and RVC - Construction of IBBelle and thermal mockup - Work on service (cable routing) C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 18
AIM: VXD Installation CAD of MPI mockup Final design /construction progressing well e.g. new design of positioning pins at CDC wall and torsion ‐ free sliding ‐ in of VXD C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 19
The Thermal Mock-up at DESY Cables for Pt100s QCS The thermal mock ‐ up: optimize the cooling system for the VXD 2 phase CO 2 to cool ASICs Colde N2 to cool Cables for FBGs sensors / Switcher Pt100s to monitor temperatures PXD Fiber Sensors (FBG) Power supply for temperature and humidity FBGs Pt100s Status: CO2 and N2 ready Pt100s / FBGs ready Power supply of PXD in preparation CO2/N2 tubes SVD ladders being prepared C. Kiesling, 8th VXD Workshop, Trieste, Sep. 9 ‐ 11, 2015, Plenary 20
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