Status of CLICdp pixel-detector readout systems Adrian Fiergolski Adrian.Fiergolski@cern.ch on behalf of the LCD vertex team CERN, EP-LCD 21 January 2016 Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 1 / 16
Overview of the readout systems 1 Idea of the multi-chip DAQ chain 2 Timepix3-based telescope 3 Summary 4 Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 2 / 16
Overview of the readout chips ASIC Readout system Telescope Integration AIDA Mimosa telescope, CLICpix + planar / CCPDv3 µ ASIC Timepix3 telescope CLICpix2 + planar / C3PD µ ASIC 2.0 Timepix3 telescope Timepix FITPix AIDA Mimosa telescope AIDA Mimosa telescope, Timepix3 CERN board/NIKHEF board + SPIDR Timepix3 telescope Cracow SOI µ ASIC 2.0 (t.b.c.) Timepix3 telescope (t.b.c.) Investigator v1 (Alice) ? t.b.c. t.b.c. [ Black: done, blue: planned ] µ ASIC FITPix SPIDR Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 3 / 16
µ ASIC — CLICpix DAQ chain FPGA board — Digilent Atlys Xilinx Spartan-6 1 Gbps Ethernet high speed VHDCI connector S. Kulis Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
µ ASIC — CLICpix DAQ chain µ ASIC board 8 × general purpose power supplies ◮ Maximum current 0.5 A ◮ Voltage range 0 – 4 V (set resolution 1 mV) ◮ Monitoring resolution : 1 mV / 25 µ A 4 × voltage output (0 — 4 V, 12 bit) 4 × current output (-100 µ A — 100 µ A, 12 bit) 4 × voltage input (0 — 4 V, 12 bit) High voltage input 12 × general CMOS signals (Input / Output). Two independent groups (8+4) with adjustable voltage level 0.9 – 3.6 V (determined by one general purpose power supply) 12 × differential pairs (Input / Output). I2C bus Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
µ ASIC — CLICpix DAQ chain Chipboard PCIe × 8 edge connector ◮ cost effective and robust solution for the R&D scenario with a single interface board and many replaceable chipboards integrated CCPDv3 board temperature sensor small memory with a unique ID S. Kulis Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 4 / 16
CLICpix2 improvements with respect to the CLICpix design: CLICpix CLICpix2 Matrix size [pixels] 64 × 64 128 × 128 Active area [ mm 2 ] 1.6 × 1.6 3.2 × 3.2 ToT counter 4 bits 5 bits ToA counter 4 bits 8 bits better noise isolation readout protocol based on Ethernet-like 640 Mbps SERDES stream P. Valerio, E. Santin configuration over SPI protocol Status currently under verification sensors are coming ◮ planar sensors with matching footprint already produced ◮ matching active HV-CMOS sensor C3PD is being finalised submission of the chips planned in the first half of this year Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 5 / 16
Requirements for the CLICpix2 readout Interface board — a new µ ASIC possibly VHDCI (FMC to VHDCI converter on the FPGA motherboard) PCIe × 8 general purpose power supplies (voltage and current outputs) with monitoring capabilities covering CLICpix2 requirements: 1.0 V VDDD , 1.2 V VDDA , 1.2 V VSSA CML , 2.5 V VDD CMOS high voltage input 1 × unidirectional SERDES link 8 × LVCMOS (2.5V, 1.2V) signals (I/O) 4 × CML differential pairs (I/O) clock and trigger/shutter input (RJ45 compatible with TLU) support of the C3PD sensor (slow control, readout of test pixels) I2C bus Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 6 / 16
SPIDR — Timepix3 readout FPGA board — VC707 Xilinx Virtex-7 2 HPC FMC connectors 10 Gbps data link soft-core Leon processor for slow control Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 7 / 16
SPIDR — Timepix3 readout interface board + chipboard two flavours: ◮ integrated interface and chipboard developed at NIKHEF ◮ separated by VHDCI connector interface and chipboard developed at CERN FMC connector 8 × 640 Mbps SERDES links power domains: 1.5 V VDD , 1.5 V VDDA , 1.5 V VDDPLL FEASTMP pluggable radiation and magnetic field tolerant 10 W DC/DC converter module Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 7 / 16
Proposal for the multi-chip DAQ chain Features: CLICpix2/Timepix3/FEI4/MuPix/... support ◮ set of simple PCIe chipboards provided by users Zynq firmware and the interface board developed by collective effort ◮ collaboration with CaRIBOu project (Brookhaven National Lab, University of Geneva, CERN) FPGA and memory can be placed in a safe distance ( ∼ 50 cm) from the sensor assembly, to prevent radiation damage from sources or particle beams and facilitate mounting voltage regulators are close to the chip Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 8 / 16
ZC706 Advantages: SoC (Z-7045) FMC HPC connector (8 GTX transceivers) FMC LPC connector (1 GTX transceiver) SFP+ connector availability cost effective and rapid solution for a small volume Usage: The integrated dual core ARM Cortex-A9 processor will run Linux OS providing Slow Control service via the Gigabit Ethernet interface. Data readout through 10 Gbps Ethernet (SFP+). Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 9 / 16
✞ ☎ Requirements for multi-chip open source µ ASIC 2.0 ✝ ✆ ✄ � FMC mezzanine ✂ ✁ ◮ 400 pins vs legacy 68-pin VHDCI ✄ � PCIe × 16 receptacle for the chipboard ✂ ✁ ◮ 164 pins vs legacy 98-pin or 80-pin SEAM connector ◮ × 8 compatible with × 16 ◮ simple adapters, ex. PCIe edge to VHDCI (CERN Timepix3) 8 × general purpose power supplies with monitoring capabilities ◮ Maximum current: 4 A ◮ Voltage range 0 — 4 V 8 × voltage output (0 — 4 V) 4 × current output (0 — 100 µ A) 4 × voltage input (0 — 4 V) FEASTMP support high voltage input ✄ � 8 × full-duplex SERDES links ✂ ✁ ADC (8 channels, 80 MSPS/12-bit) 16 × general CMOS signals (I/O) with adjustable voltage levels differential pairs (I/O) — CML converters only on the specific chipboards clock and trigger/shutter input (RJ45 compatible with TLU) I2C bus Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 10 / 16
Timepix3-based telescope With help from the LHCb Velo upgrade group, a Timepix3 telescope setup has been built and is permanently installed at the end of the SPS-H6 beamline. SPIDR readout boards from NIKHEF, mounted outside a light-tight enclosure 6-8 telescope planes, ◮ with 300 µ m thick p-in-n sensors rotated ◮ tilted by 9 ◦ in order to enhance charge sharing trigger for non self-triggered DUTs ◮ 3 × scintillators + PMTs (HAMAMATSU H10721) 2 axes + rotation stage (Newport GTS70, GTS30V, URS50BCC, ESP301-3N) Rack-mounted readout server ◮ 16 cores, 32 GB RAM, 24 TB RAID-6 disk array, ◮ 8 × 10 Gbps Ethernet (10 Gbps link to EOS, Castor) Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 11 / 16
Timepix3-based telescope — diagram Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 12 / 16
Timepix3-based telescope — performance 3 × 10 timing resolution: ≈ 1 ns 300 σ = 2.3ns spatial resolution: ≈ 2 µ m 200 particle rate: ≈ 1 . 5 × 10 6 / spill (depends on beam configuration) 100 ◮ maximum rate ≈ 10M tracks / spill -9 × 10 0 (Timepix3 limitation) -10 -5 0 5 10 t_hit - t_track / s Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 13 / 16
Timepix3-based telescope — DAQ software (1) CLIC-specific extension has been added to the LHCb readout software: parameter scans: threshold, bias, translation/rotation support of the telescope-specific infrastructure: ◮ HV Keithley power supplies Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 14 / 16
Timepix3-based telescope — DAQ software (1) CLIC-specific extension has been added to the LHCb readout software: parameter scans: threshold, bias, translation/rotation support of the telescope-specific infrastructure: ◮ HV Keithley power supplies Set of Python scripts developed by the Timepix3 designers (Xavier Llopart) alternative way to perform chip equalization and calibration Future work: integration of the telescope with the EUDAQ 2.0 software ◮ producer implements FSM and follows commands distributed by run control over TCP ◮ data stored directly by the producer consolidation of the Timepix3 DAQ source code (C++ and Python library) Adrian Fiergolski (CERN, EP-LCD) Status of CLICdp pixel-detector readout systems 21 January 2016 14 / 16
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