Development of SiTCP Based Readout System for Pixel Detector Upgrade in ATLAS Experiment Teoh Jia Jian Master 1st Year Yamanaka Taku Lab 19 Dec 2011 Monday, December 19, 2011 1
Overview -IBL & S-LHC -New FE chip ATLAS Pixel Detector Upgrade -New r/o system SiTCP Based R/O system -System Interface Module’s Setup -What & why SiTCP? Status & Plan Summary Monday, December 19, 2011 2
① Intro: ATLAS Pixel Detector Upgrade IBL = Insertable b-layer FEi4 mounted on beam pipe 3.7cm IBL new beam pipe 5cm present 3 barrel layers Phase 1 (~2015): upgrade to configuration which can eventually deliver 3x10 34 cm -2 s -1 . Inefficiency [%] Phase 2 (~2019): upgrade to enable SuperLHC (sLHC) sLHC IBL luminosity of 10 35 cm -2 s -1 . total inefficiency is no longer tolerable FEI3 at r=3.7cm! Need for a new FE chip FEI4 LHC The “inefficiency wall” New r/o system is needed!!! Hit rate / DC Source: Characterization of ATLAS Pixel Redout Chip Prototypes for high Luminosity Operation of the LHC, Hubertus Junker,, Uni. of Bonn. Monday, December 19, 2011 3
Intro: FEi4 Chip 18x160=2880 pixels 80x336=26880 pixels Active area: 74%. 10.8mm Active area:~90%. All Hits FE-I3: All hits go to periphery (column drain architecture). in-pixel storage 19mm FE-I4: local “in-pixel” storage All Hits + trigger propagated up the Triggered hits array. 7.6mm trigger data out At 3 x LHC full lumi, ineff: ~ 0.6% New features buffering � Biggest chip in HEP to date 20mm � Greater fraction of the footprint devoted to pi trigger data out array. � Lower power comsumption, 10 µ W/pixel (un-triggered hits do not move) � Able to take higher hit rate (store the hits locally in each pixel and distribute the trigger) � No need for extra module control chip (significant digital logic blocks on array periphery) Monday, December 19, 2011 4
② R/O System Interface Multi-chip Multi-chip SEABAS ( S oipix E v A luation B o A rd with S itcp) Multi-chip Single module Multi-chip Single module Multi-chip Single module Chip Single or module Chip Single module Chip One built-in SiTCP FPGA & user FPGA. Chip Chip Developed by Tomoshida Uchida (KEK). What is SiTCP? - a hardware-based TCP processor. Adapter Cards - designed for devices limited by hardware size (FE devices or detectors). FPGA Why SiTCP? (User Specified - can be implemented on a Firmware) single chip due to small SiTCP circuit size. Software (standard) - high speed data transfer Ethernet SEABAS (1Gb/s). PC Xilinx Virtex 4 Board Monday, December 19, 2011 5
Software Structure SEABAS Trigger & Software Fast Cmd SiTCP CMD SiTCP FPGA Generator Controller PC Slow Cmd User FPGA Routines Terminal Data 8b/10b Output Acquisition Decoder FEI4 Root File Generator Header Data Record Trailer Data stream: 11101... 001011101... 1000000... Monday, December 19, 2011 6
Firmware Structure SEABAS Data Receive SiTCP FIFO SiTCP Communicator FPGA LV1 Trigger CAL Pulse Configuration FEI4 State Machine Job Manager Decoder Clock Reset/Sync Generator State Machine Firmware User Top Module FPGA Firmware is written in Verilog HDL. PC Monday, December 19, 2011 7
③ Module’s Setup FEI4 Chip module Ethernet to PC SiTCP user FPGA FPGA Sub Adapter Card Card Power Power in in SEABAS Board Monday, December 19, 2011 8
④ Status & Plan Phase I: Software and firmware development. ✓ COMPLETED * Special thanks to Yosuke Takubo-san (KEK). Phase II: FEi4 chip configuration and debuging. IN PROGRESS - Read/write global reg. ✓ - Read/write pixel reg. ✓ - A.CAL pulse and L1. ✓ - Data receiving. ✓ - 8b/10b data decoding. ✓ Occupancy Show Stopper digital injection 1 Trigger 3 rd Phase III: Data acquisition, test and fine tuning. TO DO semester Monday, December 19, 2011 9
⑤ Summary Skeleton of firmware and software is complete, more functionality will be added. Now proceed to operate the chip especially to get the digital injection up and running. Aim to get reasonable hit distribution using analog and digital injection test. Monday, December 19, 2011 10
Backup Slides Monday, December 19, 2011 11
LuminosityPublicResults (21-Nov-2011, JamieBoyd) *only the peak luminosity during stable beam periods is shown. Monday, December 19, 2011 12
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SLAC RCE System Bonn USBPix System Monday, December 19, 2011 14
8b/10b Encoding The default output mode of the chip is 8b/10b encoded. - provides data framing and phase alignment. 8b/10b encoding - allows recovery of the 160MHz clock from the data stream in the BOC/ROD in the control room. An 8b/10b coder maps the 256 possible “symbols” of an 8-bit word into a specific subset of the 1024 symbols possible for a 10-bit word. The selected 10b symbols have some favorable engineering properties: - Each 10b word is either perfectly DC-balanced, or has a disparity of +2 or -2. The disparity of a word is defined as the number of 1’s minus the number of 0’s. - There is always perfect DC balance over 20 bits. The coder keeps track of DC balance by evaluating a running disparity and compensates for positive or negative disparity with the next word sent. - The coder can also generate 12 symbols which have a special meaning, in that they are decoded as commands. These commands are shown in Table 18. These symbols do not have an 8b representation, they only are possible after the 10b encoding. Monday, December 19, 2011 15
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