SOC Laboratory Course in NCTU – Trial Run Report Speaker: Kun-Bin Lee Directed by Prof. Chein-Wei Jen Department of Electronics Engineering National Chiao Tung University {kblee, cwjen}@twins.ee.nctu.edu.tw Jul. 15, 2003
Lab Modules of SOC Laboratory (1/2) 0. SOC Overview and ARM Integrator: ARM architecture, ARM-based SOC and Development tools Institute of Electronics, National Chiao Tung University 1. Code Development: Compiler, Assembler, Linker, and ARM/Thumb Code Inter-working SOC Laboratory Course in NCTU – Trial Run Report 2. Debugging and Evaluation: Debugging, Single-step, and Breakpoint, Instruction Simulator (ARMulator), Cycle Count, Timing Measurement, Profiler, and User’s Models 3. Core Peripherals: Software Modeling for Interrupt Controller, Counter/Timer, Reset, and Pause Controller 4. Real-Time OS: Driver, Function Kernels, Scheduler, API, and Communication/Memory Management 1
Lab Modules of SOC Laboratory (2/2) 5. On-chip Bus: AHB, APB, Bus Bridge, Arbiter, and VCI Interface Institute of Electronics, National Chiao Tung University 6. Memory Controller: On-chip SRAM, DMA Controller, and External Memory Interface 7. ASIC Logic: Acceleration Building Blocks, FPGA Designs and SOC Laboratory Course in NCTU – Trial Run Report Design Reuse, Generator/Configuration 8. Standard I/O: GPIO, UART, USB, 1394, Keyboard, Mouse, Button/Switch, Touch screen, and Sensor 9. JTAG and Multi-ICE: Test Access and System Debugging 10.Case Design for Term project:JPEG2000, MPEG2, xDSL, IEEE 802.11x, or Bluetooth 2
Process of the Lab Course • Affiliate with the course: IP Core Design Institute of Electronics, National Chiao Tung University – http://twins.ee.nctu.edu.tw/courses/ip_core_01/index.html 2001.9~2002.1 39 students, 5 TAs SOC Laboratory Course in NCTU – Trial Run Report – http://twins.ee.nctu.edu.tw/courses/ip_core_02/index.html 2001.9~2002.1 41 students (exclude 7 withdrawers), 4 TAs • Lab schedule – Four labs/assignments every two weeks – Pick one application and go through the assignments – Final exam is affiliated to IP Core Design 3
Lab Organization in NCTU Application Institute of Electronics, National Chiao Tung University Getting Start with ADS Working with AXD Profiling Software Quality Measurement SOC Laboratory Course in NCTU – Trial Run Report Virtual Prototyping ARM Integrator Coding Embedded SW Authoring Environment Guideline RTOS Digital IP Authoring Coverage-Driven µ HAL Driver µ C/OS-II Verification Rapid Prototyping 4
Code Development • Goal • Steps Institute of Electronics, National Chiao Tung University – How to create an – Basic software application using ARM development (tool chain) Developer Suite (ADS) flow – How to change between SOC Laboratory Course in NCTU – Trial Run Report – ARM/Thumb Interworking ARM state and Thumb • Requirements and state when writing code for different instruction sets Exercises • Principles – See next slide – Processor’s organization • Discussion – ARM/Thumb Procedure – The advantages and Call Standard (ATPCS) disadvantages of ARM and • Guidance Thumb instruction sets. – Flow diagram of this Lab – Preconfigured project stationery files 5
Code Development (cont’) • ARM/Thumb Interworking Institute of Electronics, National Chiao Tung University – Exercise 1: C/C++ for “Hello” program • Caller: Thumb SOC Laboratory Course in NCTU – Trial Run Report • Callee: ARM – Exercise 2: Assembly for “SWAP” program, w/wo veneers • Caller: Thumb • Callee: ARM – Exercise 3: Mixed language for “SWAP” program, ATPCS for parameters passing • Caller: Thumb in Assembly • Callee: ARM in C/C++ 6
Debugging and Evaluation • Goal Institute of Electronics, National Chiao Tung University – A variety of debugging tasks and software quality evaluation • Debugging skills – Set breakpoints and watchpoints SOC Laboratory Course in NCTU – Trial Run Report – Locate, examine and change the contents of variables, registers and memory • Skills to evaluate software quality: – Memory requirement of the program – Profiling: Build up a picture of the percentage of time spent in each procedure. – Evaluate software performance prior to implement on hardware – Thought in this Lab the debugger target is ARMulator, but the skills can be applied to Multi-ICE/Angel with the ARM development board(s). – The instructions are based on the Dhrystone test software 7
Debugging and Evaluation • Requirements and Exercises • Principles – Optimize 8x8 inverse discrete Institute of Electronics, National Chiao Tung University – The Dhrystone Benchmark cosine transform (IDCT) [1] – CPU’s organization according to ARM’s architecture. • Guidance SOC Laboratory Course in NCTU – Trial Run Report – Deliverables – Steps only • Discussion • Steps – Explain the approaches you apply to minimize the code – Debugging skills size and enhance the performance of the lotto – Memory requirement and program according to ARM’s Profiling architecture. – Virtual prototyping – Select or modify the algorithms of the code segments used in – Efficient C programming your program to fit to ARM's architecture. – SIMD operations in ARM core 8
In ARM CPU JTAG and non-AMBA signals Institute of Electronics, National Chiao Tung University EmbeddedICE & JTAG CP15 ARM Core SOC Laboratory Course in NCTU – Trial Run Report Physical Address AMBA MMU Address AMBA Virtual Address Interface AMBA Inst. & data Data Write Inst. & data cache Buffer 9
Software Quality Measurement • Memory Requirement Institute of Electronics, National Chiao Tung University – Data type: Volatile (RAM), non-volatile (ROM) – Memory performance: access speed, data width, size and range • Performance Benchmarking SOC Laboratory Course in NCTU – Trial Run Report – Harvard Core • D-cycles, ID-cycles, I-cycles – von Newman Cores • N-cycles, S-cycles, I-Cycles, C-Cycles – Clock rate • Processor, external bus – Cache efficiency • Average memory access time = hit time +Miss rate x Miss Penalty • Cache Efficiency = Core-Cycles / Total Bus Cycles 10
Virtual Prototyping • Features Institute of Electronics, National Chiao Tung University – Trade-off by modifying CPU Debugger (GUI) system parameters & checking results SOC Laboratory Course in NCTU – Trial Run Report – Develop & test device CPU ISS CPU ICE drivers Memory UART – Test the correctness of Rapid Model Model Prototype compiler generated code USB Intr cntrl Model Model – Visualize behavior of system and peripherals Codec Parallel I/O Model Model – Test the correctness of BLC Timer application algorithms Model Model 11
Virtual Prototyping Environment ARMulator startup banner : System Output Monitor - RDI Log Default MCCFG = 3 Institute of Electronics, National Chiao Tung University ARMulator ADS1.1 [Build 709] ARM940T, 4kB I-cache, 4kB D-cache, 10.00MHz core clock , (Physical memory, 3.3MHz , 4GB), Little endian, Debug Comms Channel, Mapfile, Timer, Tube, Profiler, SOC Laboratory Course in NCTU – Trial Run Report Pagetables, IntCtrl, Tracer, Millisecond [3333.33 cycles_per_millisecond], Semihost ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter ADS v1.1 Memory map: 00000000..7fffffff, 32-Bit, wr, wait states: RN=0 WN=0 RS=0 WS=0 RIS=0 WIS=0 ARMulator ADS1.2 [Build 805] ARM940T, 4KB I-cache, 4KB D-cache, 200.00MHz FCLK , (Physical memory, BIU), Little endian, Semihosting, Debug Comms Channel, 66.7MHz , 4GB, Mapfile, Timer, Profiler, Tube, Millisecond [66666.7 cycles_per_millisecond], Pagetables, IntCtrl, Tracer, RDI Code sequences ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter ADS v1.2 [Build number 805]. 12
Core Peripherals • Goal • Steps – Understand the HW/SW Institute of Electronics, National Chiao Tung University – The same to that of code coordination development • Memory-mapped device • Requirements and • Operation mechanism of SOC Laboratory Course in NCTU – Trial Run Report polling and Timer/Interrupt Exercises • HAL – Understand available resource – Use timer to count the total of ARM Integrator data transfer time of several • semihosting data references to SSRAM • Principles and SDRAM. – Semihosting • Discussion – Interrupt handler – Compare the performance – Architecture of Timer and Interrupter controller between using SSRAM and • Guidance SDRAM. – Introduction to Important functions used in interrupt handler 13
Lint and Coding Guideline • Syntax and semantic checks that ensure compliance with Institute of Electronics, National Chiao Tung University VHDL (IEEE 1076-1993) and Verilog (IEEE 1364/OVI 1.0, 2.0) HDL language standards • Coding checks that analyze the HDL for simulation, SOC Laboratory Course in NCTU – Trial Run Report synthesizability, design-for-reuse, and test requirements • Design practice checks that include hierarchy, combinatorial loops, reset/clocking styles and many more • Style, documentation, and naming checks that ensure adherence to coding guidelines • In this Lab: VN-Check from TransEDA Verification Navigator 14
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