SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip - PowerPoint PPT Presentation

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks A. Ejlali*, B. M. Al-Hashimi † † Electronics and Comp. Science * Computer Engineering Dept. University of Southampton Sharif University of Technology Southampton, UK Tehran, Iran

Overview • Introduction – Pipelined On-Chip Interconnects – Addressed Problem • Energy Recovery Circuits • Energy Recovery Pipelined Interconnects – Proposed Designs • Experiments 2

Pipelined On-Chip Interconnects IN OUT DFF DFF DFF DFF A 1 A 2 A 3 A 4 • Increased throughput • Freedom in choosing arbitrary topologies –Pipelining decouples the throughput from the interconnect length. 3

Addressed Problem • Reliability of on-chip interconnects – In DSM technologies, flip-flops are susceptible to SEUs. • Energy consumption of on-chip interconnects – Up to 50% of the total on-chip energy – SEU tolerance and low energy are at odds. • In this work: Specialized energy recovery designs to achieve both the above objectives at the same time 4

Previous Works 1) Energy recovery techniques for long wires - Voss et al., 2000. - Lyuboslavsky et al., 2000. These works have not considered: - reliability issues - pipelined interconnects 2) Traditional Energy Recovery Logic Styles - Eight-phase dual-rail logic - 2LAL They are not suitable for pipelined on-chip interconnects. 5

The Principle of Energy Recovery • Conventional CMOS gates (Constant voltage charging) 1 = 2 E C V Conv L DD 2 • Energy recovery CMOS gates (Constant current charging) RC = 2 L E ( ) C V − Cons Cur L DD T RF V in Clock Period VDD C L V A V in GND Charge Discharge T R T F 6

Characteristics of Energy Recovery Circuits • The trapezoidal signals provide – Operating power – Timing information (power-clocks) • Essentially pipelined sequential circuits • Multiphase trapezoidal power-clock signals • Reversible logic functions 7

Energy Recovery Pipelined Interconnects P 0 P 1 P 2 P 3 P 0 P 1 1 = ⋅ C C + Stage L n 1 • Constant current charging of the non-pipelined interconnect RC = 2 L E C V − non pipelined L DD T RF • Constant current charging of the pipelined interconnect ⎡ ⎤ RC 1 RC = ⇒ = + = ⋅ Stage 2 2 L ⎢ ⎥ E C V E ( n ) ( n 1 ) E C V + Stage Stage DD pipeline Stage L DD ⎣ ⎦ T n 1 T RF RF 8

Energy Saving via Pipelining • Conventional pipelined interconnects: – Depth of pipelining ⇑ ⇒ Throughput ⇑ • Energy recovery pipelined interconnects: – Depth of pipelining ⇑ ⇒ Throughput ⇑ • T RF decreases – Depth of pipelining ⇑ ⇒ Energy consumption ⇓ • T RF remains unchanged 9

Proposed Designs • ER – Energy Recovery Pipelined Interconnects • Energy Saving: 50% • Reliability: Slightly less reliable than conventional pipelines • SHER – SEU-Hardened and Energy Recovery Pipelined Interconnects • Energy Saving: 30% • Reliability: Considerably hardened against SEUs Disadvantages of Traditional Energy Recovery Logic Styles – Eight-phase dual-rail logic • 8 power-clock signals – 2LAL • Floating nodes • Problems in DSM technologies – SEU-Hardness has not been considered 10

ER Buffer V DD A i+1 • Dual-rail logic A i • 4 power-clocks P j A i-1 A i-1 • Circuit parts: A i-1 A i – Transmission gates A i A i – Transistor stack P j-1 P j P j-1 P j P j A i-1 P j-1 A i-1 A i A i-1 A i ER A i Buffer A i-1 A i A i-1 P j-1 A i+1 A i+1 A i A i+1 11

12 C Clamp Transistor Stack B B C D P j+1 P j • Two consecutive buffers B C A A B C P j P j-1 B A

ER Pipelined Interconnects A 3 A 3 P 3 P 3 P 0 A 4 Buffer ER P 1 P 2 A 4 P 2 P 2 A 2 A 2 P 3 P 2 P 2 IN 1 0 1 1 0 0 A 3 Buffer ER P 1 IN A 3 P 1 A1 A 1 A 1 A1 P 1 P 1 A 2 Buffer A2 ER P 0 A 2 A3 P 0 Time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 IN IN A detailed example in Pages 4 and 5 of the paper 13

SEU-Hardness A 3 A 3 P 3 P 3 P 0 Hardened A 4 Buffer ER P 1 P 2 A 4 Sensitive P 2 P 2 A 2 A 2 P 3 P 2 P 2 IN A 3 Buffer ER P 1 IN A 3 P 1 A1 A 1 A 1 P 1 P 1 A1 A 2 Buffer A2 ER P 0 A 2 A3 P 0 Time IN IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 14

Voltage Inverse vs. Logical Inverse Clock Period #1 #2 #3 #4 #5 P P A A ~A A ¯ = voltage inverse of A, ~A=logical inverse of A 15

SHER Buffer V DD P j A i ~A i-1 -1 A i-1 • 4-rail logic ~A i ~A i ~A i • 4 power-clocks P j-1 P j • Circuit parts: ~A i-1 ~A i-1 ~A i – Transmission gates ~A i A i P j-1 – Clamp transistor V DD ~A i P j A i-1 A i-1 P j-1 P j P j P j-1 A i A i A i ~A i-1 ~A i P j-1 ~A i-1 ~A i SHER P j Buffer A i-1 A i-1 A i A i-1 A i A i-1 A i A i ~A i P j-1 16

SHER Pipelined Interconnects ~A 3 ~A 3 A 3 A 3 P 0 P 3 P 3 P 1 Buffer SHER P 2 P 2 P 3 P 2 IN ~A 2 ~A 2 A 2 A 2 P 2 P 2 IN Buffer SHER ~IN P 1 ~IN P 1 A1 ~A 1 A 1 A 1 ~A 1 ~A1 P 1 P 1 A2 Buffer SHER P 0 ~A2 A3 P 0 ~A3 ~IN ~IN IN IN Time 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A detailed example in Pages 6, 7 and 8 of the paper 17

Experimental Evaluation • SPICE simulations – 45nm PTM technology • Interconnect – C L =1pF • About 5 millimeters long wire in 45nm technology V DD – Throughput = 0.1 Gbps P j A i • Estimating energy consumption ~A i-1 -1 A i-1 ~A i – A random bit string consisting of 120 bits ~A i • Estimating reliability against SEUs ~A i I Inj P j-1 – Faults were injected using current sources t − 2 Q t = ⋅ ⋅ ⋅ I ( t ) e T π Inj T T 18

Energy Consumption of Pipelined On-Chip Interconnects Pipelining # of FFs or Average Power Energy consumption * (pJ) Scheme # of Buffers (uW) 11.90 Conventional 3 FFs 14.28 12.14 4 FFs 14.57 12.42 5 FFs 14.91 7.42 ER 12 BUFs 8.90 16 BUFs 6.36 7.63 20 BUFs 5.56 6.67 SHER 12 BUFs 11.22 13.47 16 BUFs 9.62 11.54 20 BUFs 8.41 10.09 * The energy consumption when a bit string with 120 random bits is transmitted 19

Results Obtained From the Fault Injection Experiments Pipelining Scheme # of FFs or # of SEUs % of SEUs * # of Buffers Conventional 3 FFs 377 9.2 4 FFs 618 15.08 792 5 FFs 19.33 ER 12 BUFs 502 12.26 16 BUFs 816 19.92 20 BUFs 844 20.61 SHER 12 BUFs 0 0 16 BUFs 0 0 20 BUFs 2 0.05 * 4096 faults (simulated particle strikes) were totally injected 20

Summary • We have proposed the use of energy recovery techniques to construct low energy and reliable pipelined on-chip interconnects. • We have presented two energy recovery designs: – ER • Energy Saving: 50% • Reliability: Slightly less reliable than conventional pipelines – SHER • Energy Saving: 30% • Reliability: Considerably hardened against SEUs 21

Future Works • Analyzing the use of frequency scaling: RC = 2 L E ( ) C V − Cons Cur L DD T RF • Analyzing the throughput/energy trade-off – Depth of pipelining ⇑ ⇒ Throughput ⇑ • T RF decreases – Depth of pipelining ⇑ ⇒ Energy consumption ⇓ • T RF remains unchanged 22

23 Thank You