Report on WP4 Activities P. Riedler, CERN ITS Pleanry -WP4, P. - PowerPoint PPT Presentation

Report on WP4 Activities P. Riedler, CERN ITS Pleanry -WP4, P. Riedler, 20.1.2014 1

WP4 Meetings: bi-weekly on Tuesday 16:00 (GVA time) Next Meeting: January 28, 2014 at 16:00 At CERN: 160-R-009 ITS Pleanry -WP4, P. Riedler, 20.1.2014 2

WP4 Activities and Objectives for 2014 1. Wafer procurement and QA Finalize strategy for procurement and survey of high-res wafers 2. Wafer post processing Definition and qualification of process steps 3. Thinning and dicing Selection and qualification of thinning and dicing process and procedure 4. Interconnection R&D Selection of chip interconnection process (laser soldering or spTAB) 5. Mass tests Define mass-production test procedure and develop prototype set-up 6. Procurement of dummy/pad wafers in conjunction with WP3,6,7,8,9 ITS Pleanry -WP4, P. Riedler, 20.1.2014 3

1. Wafer procurement and QA Finalize strategy for procurement and survey of high-res wafers Choice of starting wafer material • Used different high-res epi wafers in engineering run March2013 • Choice will depend on test results of prototype chips (see WP5): • Epitaxial layer thickness • Epitaxial layer resistivity • Some custom high-res wafers are still available; if new ones are required they need to be ordered now. • Procurement of the wafers for the production should start end of 2014/beginning of 2015 Table 3.1: Wafers used for the engineering run March 2013. Goals: Type Number of wafers Epitaxial Thickness ( µ m) Resistivity (k Ω cm) 1 (LR-12) 3 12 . 0 ± 0 . 5 0 . 03 • Finalize choice of high-res wafers by end summer 2014 2 (HR-18) 4 18 . 0 ± 1 . 5 > 1 3 (HR-30) 3 30 . 0 ± 0 . 3 ≈ 1 4 (HR-40A) 3 40 . 0 ± 0 . 6 ≈ 1 • Finalize QA by end of 2014 5 (HR-20) 6 20 . 0 ± 1 . 9 6 . 2 6 (HR-40B) 3 40 . 0 ± 1 . 9 7 . 5 7 (CZ) 3 CZ > 0 . 7 ITS Pleanry -WP4, P. Riedler, 20.1.2014 4

Wafer QA before processing Data supplied by vendor for custom wafers: epitaxial layer thickness and resistivity QA activities started with TMEC (sample basis): ü SEM cross-section inspection ü Surface resistivity measurement • SRP measurement of resistivity profile in the epi layer SEM cross-section Surface resistivity map ITS Pleanry -WP4, P. Riedler, 20.1.2014 5

Wafer QA after processing Main task: Basic visual inspection on the wafers, i.e. the connection pads , prior to • Post-processing and/or • Thinning and dicing Rockwood carries out visual entrance inspection for other customers (i.e. inspection of one die in x locations of a wafer) Proposal is in preparation (limit time/cost). Inspection procedure to be tested on next wafers to be diced (Feb. 2014) ITS Pleanry -WP4, P. Riedler, 20.1.2014 6

2. Wafer post-processing Definition and qualification of process steps To apply solder on the Al pads the pad needs to be covered with a wet-able metal (i.e. Ni) which is protected from oxidation (Au). The quality of the Ni/Au layer is important to ensure a good soldering connection. Several pad chip wafers have been produced (IZM, TMEC) with Ni/Au pads. In addition Al pad chips have been plated with Ni/Au at CERN. Tower does not provide this service but has an external supplier that provides Ni/Au coating for their products (PacTECH). Goals: • Contact PacTECH and discuss plating of wafers (January 2014) and time-schedule for subsequent tests. • Send few pad wafers from the presently processed run to PacTECH for Ni/Au plating (~Feb. 2014) and do soldering tests. • TBD: Send engineering run wafer with pALPIDE-FS to PacTECH and carry out soldering tests (~April 2014). • Finalize process steps and prepare document (end 2014). ITS Pleanry -WP4, P. Riedler, 20.1.2014 7

3. Thinning and dicing Selection and qualification of thinning and dicing process and procedure Until now 35 8” wafers and 16 6” wafers have been thinned and diced to 50 (70) um by Rockwood using diamond wheel pre-dicing before grinding. First blank wafers diced and thinned by STARS received last week (laser dicing) – metrological checks ongoing. Requirements: Thickness: 50 um ± 5 um, dimensions: ±30 um (TDR) need to be revised wrt FPC precision Goals: • Prepare thinning and dicing of pad and engineering run wafers for Feb/March 2014 (dates agreed with Rockwood) – fast track for first engineering run wafer. • Special dicing wheel will be used for next wafers to reduce chipping and precision (potentially possible to achieve 10 um) ~March/April 2014 – evaluate precision and chipping. • Evaluate laser dicing as option (to be tested on high-res epi wafer) ~summer 2014 • Gradually review QA procedures and implement final protocol (e.g. including now visual inspection for incoming wafers at Rockwood) ~ end 2014 ITS Pleanry -WP4, P. Riedler, 20.1.2014 8

Blank wafer Laser diced by STARS ER2013 wafer Blank wafer Diamond wheel dicing Laser diced (2000 mesh wheel) (front view) ITS Pleanry -WP4, P. Riedler, 20.1.2014 9

5. Interconnection R&D Selection of chip interconnection process (laser soldering or spTAB) Goals: • Produce sufficient number of samples for evaluation • Detailed analysis of the two techniques based on samples close to the final layout • Decision process to be started before summer 2014 • Since September a laser soldering station is installed at the CERN DSF. • Systematic studies carried out to define the soldering setup and environment (jigs, gas, etc.) as well as investigation of the QA requirements for the components (pad structure, FPC, … ) • Requirements and procedures to be included in a QA document. • Tests based on pad chips with 50 contacts of 200 um diameter and corresponding FPCs ITS Pleanry -WP4, P. Riedler, 20.1.2014 10

Series of tests to validate connection • Electrical daisy-chain test of 50 contacts • Microscope inspection • Metallurgical cross-section analysis+SEM Tin QA document in preparation Intermetallic • Component requirements • Procedures Nickel • Fast and detailed analysis Palladium Aluminium ITS Pleanry -WP4, P. Riedler, 20.1.2014 11

Laser soldering Consistently excellent soldering results over the single chip flexes: • Perfect solder surface • Good attachment • No burning, no oxidation • Consistent laser power/temperature on all contacts • Only one profile used – no tweeking needed Achieved on the last 3 single chip flexes: 49.5/50 contacts – 49.5? • Only badly done FPCs available (new ones not yet returned from production) • Holes on the FPC too small (ball does not sink in) 49.5: if putting probe onto one contact – 50/50 electrical contacts 12

spTAB bonding • Pad chips for tests given to Bari, Trieste and Karkhov • Preparation of cables and first connection tests ongoing Example: Cable designed by Bari/produced by Kirana/FBK 13

5.Mass test Define mass-production test procedure and develop prototype set-up Visual inspection and functional tests Main challenges: • Handling and contacting of 50 um thick chips • Testing of a large number of components à development of automatized systems Status: 1.Visual inspection: Tests on pad chips with VEA (Italy) 2. Function tests - contact technique: • Probe-card contact (Yonsei and Corean company) • Bed of needle contact (SPEA, Italy) ITS Pleanry -WP4, P. Riedler, 20.1.2014 14

Mass test Moun%ng'of'the'chips'on'a' jig'or'chip_tray' Visual'and'metrological' inspec%on' Remove'damaged'chips' from'list'of'chips'to'test' Transfer'jig/chip_tray'to'test=sta%on' Electrical''and'func%onal'test'' Categorize'chips' Chips'for'moun%ng' Started discussion on test-flow ITS Pleanry -WP4, P. Riedler, 20.1.2014 15

5. Mass test Transport and storage of dies before and after mass test, prior to assembly is an important task. Several boxes under consideration: • Foam boxes useful for pad and dummy wafers, probably not adapted for real chips (cleanliness, outgassing,..) • Gelpak boxes with larger area (125 mm or 150 mm side-length) being investigated Goals: • Preparation of prototype mass tests using pad chips (studies ongoing). • Development of test system based on test system for full scale prototypes (together with WP3/5/10). • First functional tests with full scale prototype chips in second half of 2014. • Further investigation on how to integrate optical inspection into the test flow. ITS Pleanry -WP4, P. Riedler, 20.1.2014 16

6. Dummy and pad chips • Needed for various activities (interconnection tests, mass tests, assembly, … ) • Production of masks, processing, thinning and dicing of wafers presumably takes about 2-3 months. Dummy chips Pad chips • 15 mm x 30 mm • 15 mm x 30 mm • 50 um thick • 50 um thick • Metal pads and traces on SiO 2 /Si • Blank silicon • Daisy chain connections WP6 meeting 16/01/14 - P. Riedler

Component status • Some chips left of each type, but not sufficient for the activities in 2014! • Collect needs from the different activities and start producing dummy + pad chips – Require estimate on needs from the other workpackages Next: • Purchase wafers for dummy and pad chips. • Thin and dice wafers for dummy chips. • Pad chips: define layout and produce patterned wafers followed by thinning and dicing. WP6 meeting 16/01/14 - P. Riedler