Redundant Via Insertion Redundant Via Insertion with Wire Bending - PowerPoint PPT Presentation

Redundant Via Insertion Redundant Via Insertion with Wire Bending with Wire Bending Kuang- -Yao Lee, Yao Lee, Shing Shing- -Tung Lin and Ting Tung Lin and Ting- -Chi Wang Chi Wang Kuang Department of Computer Science Department of Computer Science National Tsing Tsing Hua Hua University University National Hsinchu, Taiwan , Taiwan Hsinchu 1 1

Outline Outline Preliminaries Preliminaries Problem definition Problem definition Minimum- -weight maximum independent weight maximum independent Minimum set formulation set formulation 0- -1 integer linear program based approach 1 integer linear program based approach 0 Experimental results Experimental results Conclusion Conclusion 2 2

Redundant via Redundant via Enable a single via failure to be tolerated Enable a single via failure to be tolerated Improve the chip yield and reliability Improve the chip yield and reliability N N Redundant Double Via Redundant Via Via W W E E Single Single via via S S 3 3

Feasible double via Feasible double via Feasible Infeasible 4 4

Wire bending Wire bending Create more feasible double vias vias Create more feasible double Improve the insertion rate Improve the insertion rate d 3 v 1 v 1 d 1 v 2 d 2 v 2 d 1 d 2 Insertion rate = 50% Insertion rate = 100% 5 5

Wire bending (cont’ ’d) d) Wire bending (cont The wires are allowed to be bent The wires are allowed to be bent A bending window of pre- -defined size is given defined size is given A bending window of pre Bending window p’ p’ Legal p p Bending window p’ p’ Illegal p p 6 6

Double via insertion with wire bending Double via insertion with wire bending (DVI/WB) (DVI/WB) Input Input – – A routed design and a set of via- -related design rules related design rules A routed design and a set of via Goal Goal 1. To replace as many single To replace as many single vias vias with double with double vias vias as as 1. possible possible 2. Minimize the Minimize the wirelength wirelength increase due to wire increase due to wire 2. bending bending Constraints Constraints – – Each single via either remains unchanged or is Each single via either remains unchanged or is replaced by a double via replaced by a double via – – After via replacement and wire bending, no design After via replacement and wire bending, no design rule is violated rule is violated 7 7

Enhanced conflict graph Enhanced conflict graph An undirected vertex- -weighted graph weighted graph An undirected vertex constructed from a detailed routing solution constructed from a detailed routing solution Vertex Vertex – a feasible double via a feasible double via – Edge Edge – cannot be inserted simultaneously cannot be inserted simultaneously – d 3 d 3 d 1 d 2 d 1 d 2 8 8

Enhanced conflict graph Enhanced conflict graph Each vertex is associated with a weight Each vertex is associated with a weight – The amount of The amount of wirelength wirelength increase caused by increase caused by – inserting the corresponding double via inserting the corresponding double via Weight = m 1 +m 2 +m 3 +m 4 Bending window m 3 m 4 m 1 m 2 p’ p’ p p 9 9

Theorem Theorem The DVI/WB problem can be formulated The DVI/WB problem can be formulated as that of finding a minimum- -weight weight as that of finding a minimum maximum independent set (mWMIS mWMIS) from ) from maximum independent set ( the enhanced conflict graph the enhanced conflict graph 10 10

Graph construction Graph construction [Lee et al., ICCAD’06] – Sweep-line-like approach – Cannot consider wire bending N1 W3 S1 N2 S3 E1 S2 E3 1 2 3 W2 W3 E2 11 11

Graph construction Graph construction 0 0 1 5 0 2 1 3 4 0 3 2 5 0 4 12 12

Graph construction Graph construction Bending window K K 6 6 0 0 1 5 0 2 K 6 0 3 0 4 13 13

Graph construction Graph construction 1 0 0 1 5 3 4 6 0 2 K 6 2 5 7 0 3 0 7 8 0 4 0 8 14 14

0- -1 ILP formulation 1 ILP formulation 0 # of single vias Weight of vertex i ∑ ∑ ⋅ − ( | SV |) Maximize C R W R i i i ≤ ≤ ≤ ≤ 1 8 1 8 i i External > max W i 0 0 1 Subject to 5 + + + ≤ 0 1 R R R R 2 K 1 2 3 4 6 + + + ≤ 1 R R R R 0 5 6 7 8 3 0 + ≤ 7 1 R R Double-cut 2 5 0 4 constraint + ≤ 0 1 R R 8 4 6 Conflict ∈ { 0 , 1 } R constraint i 15 15

Speed- -up up – – Speed Pre- -selection selection Pre Adapted from [Lee et al, ISPD’ ’08] 08] Adapted from [Lee et al, ISPD – No external edge No external edge – – Having the minimum weight among the Having the minimum weight among the – vertices coming from the same single via vertices coming from the same single via W 5 0 1 1 5 3 4 W 2 W 6 2 6 6 2 5 7 W 7 0 3 7 8 W 8 W 4 4 8 16 16

Speed- -up up – – Speed Connected components Connected components [Lee et al, ISPD’ ’08] 08] [Lee et al, ISPD – Divide into smaller 0 Divide into smaller 0- -1 ILP problems 1 ILP problems – 17 17

Overall approach Overall approach 0 10 1. Pre- -selection selection 1. Pre 1. Pre-selection 5 9 5 5 0 0 5 5 0 0 18 18

Overall approach Overall approach 1. Pre- -selection selection 1. Pre 1. Pre-selection 9 5 2.Connected Connected 2. 5 2.Connected 0 0 Components Components Components 5 5 0 0 19 19

Overall approach Overall approach ∑ ∑ ⋅ − Maximize 6 2 R W R i i i ≤ ≤ ≤ ≤ 1 4 1 4 i i Λ Subject to 1. Pre- -selection selection 1. Pre 1. Pre-selection 9 5 2.Connected Connected 2. 5 2.Connected 0 0 Components Components Components 5 5 0 0 3. Solve 0 Solve 0- -1 ILP 1 ILP 3. 3. Solve 0-1 ILP ∑ ∑ ⋅ − Maximize 10 2 R W R i i i ≤ ≤ ≤ ≤ 1 5 1 5 Λ i i Subject to 20 20

Overall approach (cont’ ’d) d) Overall approach (cont 0 10 5 9 5 5 0 0 5 5 0 0 21 21

Experiment setup setup Experiment Linux based machine with 2.4GHz processor Linux based machine with 2.4GHz processor and 2GB memory and 2GB memory Adopted lp_solve lp_solve as our 0 as our 0- -1 ILP solver 1 ILP solver Adopted Circuit #Nets #I/Os #Vias Vias #M- -Layers Layers Circuit #Nets #I/Os # #M C1 4309 20 24594 5 C1 4309 20 24594 5 C2 5252 211 41157 5 C2 5252 211 41157 5 C3 18157 85 127059 5 C3 18157 85 127059 5 C4 17692 415 151912 5 C4 17692 415 151912 5 C5 44720 99 357386 5 C5 44720 99 357386 5 22 22

Experimental results – – Experimental results Effectiveness of wire bending Effectiveness of wire bending w/o wire bending with wire bending w/o wire bending with wire bending Circuit Circuit #A- -vias vias |V| |E| T(s) ) #A- -vias vias |V| |E| T(s) ) #A |V| |E| T(s #A |V| |E| T(s C1 C1 19796 43246 36714 22 20664 53504 64083 27 C2 C2 31464 67312 54376 32 33174 90541 114497 41 C3 C3 99142 215647 179307 120 104356 284072 357643 157 C4 C4 112076 220538 159691 131 119795 302904 371024 184 C5 C5 276032 574142 444754 442 296323 804268 1025320 731 1 1 1 1 1.06 1.33 2.09 1.36 1 1 1 1 1.06 1.33 2.09 1.36 Normalized Normalized 23 23

Experimental results – – Experimental results # of inserted double vias vias # of inserted double 01ILP– –DVI* DVI* 01ILP– –DVI/WB DVI/WB 01ILP 01ILP Circuit Circuit #DVI T(s) ) #DVI #WB T(s) ) #DVI T(s #DVI #WB T(s C1 19754 3.23 20567 835 3.37 C1 19754 3.23 20567 835 3.37 C2 31411 3.30 33101 1720 3.54 C2 31411 3.30 33101 1720 3.54 C3 98888 3.81 103934 5146 4.87 C3 98888 3.81 103934 5146 4.87 C4 111657 3.87 119256 7798 5.19 C4 111657 3.87 119256 7798 5.19 C5 275437 5.14 295383 20256 13.62 C5 275437 5.14 295383 20256 13.62 1 1 1.06 - 1.18 1 1 1.06 - 1.18 Normalized Normalized *[Lee et al., ISPD’08] 24 24

Experimental results – – Experimental results Wirelength increase increase Wirelength ECG + 01ILP– –DVI* DVI* 01ILP– –DVI/WB DVI/WB ECG + 01ILP 01ILP Circuit Circuit μ m μ m WL( μ WL( μ Rate(%) T(s) ) Rate(%) T(s) ) m) ) Rate(%) T(s m) ) Rate(%) T(s WL( WL( C1 3.22E+03 0.32 3.30 9.96E+02 0.10 3.37 C1 3.22E+03 0.32 3.30 9.96E+02 0.10 3.37 C2 C2 8.21E+03 8.21E+03 0.39 0.39 3.43 3.43 2.12E+03 2.12E+03 0.10 0.10 3.54 3.54 C3 C3 2.47E+04 2.47E+04 0.39 0.39 4.42 4.42 6.30E+03 6.30E+03 0.10 0.10 4.87 4.87 C4 3.11E+04 0.32 4.41 9.79E+03 0.10 5.19 C4 3.11E+04 0.32 4.41 9.79E+03 0.10 5.19 C5 9.27E+04 0.36 9.02 2.57E+04 0.10 13.62 C5 9.27E+04 0.36 9.02 2.57E+04 0.10 13.62 1 - 1 0.28 - 1.22 1 - 1 0.28 - 1.22 Normalized Normalized *[Lee et al., ISPD’08] 25 25