Reducing SSD Read Latency via NAND Flash Program and Erase - PowerPoint PPT Presentation

Reducing SSD Read Latency via NAND Flash Program and Erase Suspension Guanying Wu and Xubin He {wug, xhe2}@vcu.edu Department of Electrical and Computer Engineering Virginia Commonwealth University Richmond, VA This research is sponsored in part by the U.S. National Science Foundation (NSF) under grants CCF-1102605 and CCF-1102624. 2/20/2012 1

Suspend Program and Erase to make Read faster? 2

Motivation • P/E (Program/Erase) are about 10x/100x slower than read. • P/E are non-suspendable in current NAND products – Once committed to NAND flash, no preemptions. • If apps write and read at the same time & Intensive workloads – Read latency suffers from queuing delay. 3

A Simple Demo RD3 wouldn’t benefit from RPS 4

Further Investigation • Comparing: – FIFO • Simulation with disk I/O traces. – Read Priority Scheduling – MS SSD-add-on simulator – Optimistic cases: – 6 popular traces • Equal latencies: PER • 0 P/E latencies: PE0 FIFO RPS PER PE0 1 SLC MLC Normalized Read Latency 0.8 0.6 0.4 0.2 0 F1 F2 DAP MSN C3 C8 F1 F2 DAP MSN C3 C8 5

Our Idea: Make NAND Flash P/E Suspendable We are expecting: 6

Outline • Background: – Why can we suspend P/E? • Design: – How do we do it? • Evaluation: – Compare to the optimistic cases • Conclusion 7

Background: NAND Flash Erase • NAND Flash Erase: – Reset cells via a long pulse of Erase Voltage to expel the electrons. – Plus a verify operation.  Guarantee the duration 4us 8us 1.5/3ms 8

Background: NAND Flash Program • NAND Flash Program: – Incremental Step Pulse Programming ARASE, K. Semiconductor NAND Type Flash Memory with 9 Incremental Step Pulse Programming, Sept. 22 1998. U.S. Patent 5,812,457.

Background: NAND Flash Program • Program pulse and verify are considered atomic • Suspend in the interval between program pulse and verify 20us 8/24us NAND Flash Program: Timeline 10

Background: NAND Flash P/E • Correct Timing – Program: what is the last phase? what is the value of Vpp? – Erase: how much job have we done/how much is left? BREWER, J.; GILL, M. Nonvolatile Memory Technologies with Emphasis on Flash . 11

Design: Suspend/Resume Erase • Case 1: Read arrives when resetting wire voltage • Case 2: Read in the middle of Erase Pulse or Verify (cancelled) 12

Design: Suspend/Resume Erase • Case 1: Suspension happens in Verify phase – Redo Verify phase. (overhead to erase latency) • Case 2: Suspension happens in Erase phase – Finish what is left before suspension. 13

Design: Suspend/Resume Program • Program pulse and Verify are considered atomic, intuitively: – Choice 1: Suspend in the intervals – I nter- P hase- S uspension – Choice 2: Cancel the current phase – I ntra- P hase- C ancellation 14

Design: Suspend/Resume Program • Need to retain the page buffer first. • Resume from IPS Overhead • Resume from IPC Overhead Overhead 15

Evaluation: Read Latency RPS PER PE0 PES_IPC 1 MLC SLC Normalized Read Latency 0.8 0.6 0.4 0.2 0 F1 F2 DAP MSN C3 C8 F1 F2 DAP MSN C3 C8 PES_IPC PES_IPS 1.15 Normalized Read Latency SLC MLC 1.1 1.05 1 0.95 0.9 F1 F2 DAP MSN C3 C8 F1 F2 DAP MSN C3 C8 16

Evaluation: Write Latency Overhead FIFO RPS PES_IPS PES_IPC 1.1 Normalized Write Latency SLC MLC 1.05 1 0.95 0.9 0.85 0.8 17

Conclusion • Suspending P/E for read is a feasible solution: – Significant read performance gain. – Low overhead on write latency. 18