pydgin for risc v a fast and productive instruction set
play

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator - PowerPoint PPT Presentation

Dec 06, 2023 •783 likes •1.46k views

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems

  1. Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems Laboratory Computer Systems Laboratory

  2. Motivation Software Instruction-Set Architecture Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  3. Motivation Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  4. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  5. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Typical DBT: 100s MIPS (1-3 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  6. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Typical DBT: 100s MIPS (1-3 hours) QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  7. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  8. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  9. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Vendor Proprietary ISA Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  10. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) RISC-V Foundation RISC-V Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  11. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) RISC-V Foundation RISC-V Software Specialized RISC-V Instruction-Set Simulator Specialized RISC-V Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  12. Productivity Performance 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  13. Productivity Performance Architectural Instruction Set Description Interpreter in C Language with DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  14. Productivity Performance Architectural Instruction Set Description Interpreter in C Language with DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  15. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT [Simit-ARM2006] J.D’Erricoand W.Qin. Constructing Portable Compiled Instruction-Set Simulators — An ADL-Driven Approach. DATE’06. [Wagstaff2013] H. Wagstaff, M. Gould, B. Franke, and N.Topham. Early Partial Evaluation in a JIT-Compiled, Retargetable Instruction Set Simulator Generated from a High-Level Architecture Description. DAC’13. 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  16. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic Language Interpreter in C with JIT Compiler 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  17. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Key Insight: Similar productivity-performance challenges for Dynamic Language building high-performance interpreters of Interpreter in C dynamic languages. with JIT Compiler (e.g. JavaScript, Python) 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  18. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Key Insight: Similar productivity-performance challenges for Dynamic Language building high-performance interpreters of Interpreter in C dynamic languages. with JIT Compiler (e.g. JavaScript, Python) 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  19. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic-Language RPython Dynamic Language Interpreter in C Interpreter Translation in RPython Toolchain with JIT Compiler 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  20. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic-Language RPython Dynamic Language Interpreter in C Interpreter Translation in RPython Toolchain with JIT Compiler Meta-Tracing JIT: makes JIT generation generic across languages 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  21. Productivity Performance Architectural Instruction Set Pydgin Description Interpreter in C Language with DBT RPython Translation Toolchain 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  22. Productivity Performance Architectural Instruction Set Pydgin Description Interpreter in C Language with DBT RPython Translation Toolchain JIT ≈ DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  23. Pydgin Architecture Description Language Architectural State State Instruction Encoding Encoding Semantics Instruction Semantics 3 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  24. Pydgin Architecture Description Language Architectural State State class State( object ): Encoding Semantics def __init__( self, memory, reset_addr=0x400 ): self.pc = reset_addr self.rf = RiscVRegisterFile() self.mem = memory # optional state if floating point is enabled if ENABLE_FP: self.fp = RiscVFPRegisterFile() self.fcsr = 0 4 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  25. Pydgin Architecture Description Language Instruction Encoding State encodings = [ Encoding Semantics # ... ['xori', 'xxxxxxxxxxxxxxxxx100xxxxx0010011'], ['ori', 'xxxxxxxxxxxxxxxxx110xxxxx0010011'], ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], ['sub', '0100000xxxxxxxxxx000xxxxx0110011'], ['sll', '0000000xxxxxxxxxx001xxxxx0110011'], # ... ] 5 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  26. Pydgin Architecture Description Language Instruction Semantics State def execute_addi ( s, inst ): Encoding Semantics s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.pc += 4 def execute_sw ( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 def execute_beq ( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4 6 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  27. Pydgin Framework Interpreter Loop State def instruction_set_interpreter( memory ): Encoding Semantics state = State( memory ) while True: Pydgin Framework pc = state.fetch_pc() inst = memory[ pc ] # fetch execute = decode( inst ) # decode execute( state, inst ) # execute 7 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  28. Pydgin Framework Interpreter Loop State def instruction_set_interpreter( memory ): Encoding Semantics state = State( memory ) while True: Pydgin Framework pc = state.fetch_pc() inst = memory[ pc ] # fetch Debug on execute = decode( inst ) # decode Python execute( state, inst ) # execute Interpreter 100 KIPS 7 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  29. The RPython Translation Toolchain RPython Source State Type Inference Encoding Semantics Op � miza � on Pydgin Framework Code Genera � on Debug on RPython Python Translation Compila � on Interpreter Toolchain 100 KIPS Compiled Interpreter 8 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  30. The RPython Translation Toolchain RPython Source State Type Inference Encoding Semantics Op � miza � on Pydgin Framework Code Genera � on Debug on RPython Python Translation Compila � on Interpreter Toolchain 100 KIPS Compiled Interpreter Pydgin Interpretive Simulator 10 MIPS 8 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

Recommend

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems

1.01k views • 24 slides
CISC / RISC Complex / Reduced Instruction Set Computers CISC / RISC p. 1/12 Instruction

CISC / RISC Complex / Reduced Instruction Set Computers CISC / RISC p. 1/12 Instruction

Systems Architecture CISC / RISC Complex / Reduced Instruction Set Computers CISC / RISC p. 1/12 Instruction Usage Instruction Group Average Usage 1 Data Movement 45.28% 2 Flow Control 28.73% 3 Arithmetic 10.75% 4 Compare

1.3k views • 12 slides
Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail in the instruction set wars? Describe a simple RISC ISA called DLX 2. Designing a simple DLX processor: Single Cycle Implementation Multiple

753 views • 11 slides
Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail in the instruction set wars? Describe a simple RISC ISA called DLX 2. Designing a simple DLX processor: Single Cycle Implementation Multiple

1.01k views • 21 slides
PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research

PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research

PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research Derek Lockhart, Berkin Ilbeyi, Christopher Batten Computer Systems Laboratory School of Electrical and Computer Engineering Cornell University

706 views • 18 slides
ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University

ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University

ARM Advanced RISC Machines The ARM Instruction Set The ARM Instruction Set - ARM University Program - V1.0 1 Processor Modes * The ARM has six operating modes: User (unprivileged mode under which most tasks run) FIQ (entered when a high

1.02k views • 75 slides
QEMU Support for the RISC-V Instruction Set Architecture Sagar Karandikar

QEMU Support for the RISC-V Instruction Set Architecture Sagar Karandikar

QEMU Support for the RISC-V Instruction Set Architecture Sagar Karandikar sagark@eecs.berkeley.edu KVM Forum 2016 https://github.com/riscv/riscv-qemu Outline Why RISC-V? Benefits of an Open ISA RISC-V ISA Basics Virtualization

536 views • 42 slides
PROCESSOR DEVELOPMENT THE FREE AND OPEN RISC INSTRUCTION SET ARCHITECTURE Codasip is the

PROCESSOR DEVELOPMENT THE FREE AND OPEN RISC INSTRUCTION SET ARCHITECTURE Codasip is the

ENHANCED TOOLS FOR RISC-V PROCESSOR DEVELOPMENT THE FREE AND OPEN RISC INSTRUCTION SET ARCHITECTURE Codasip is the leading provider of RISC-V processor IP Codasip Bk : A portfolio of RISC-V processors Uniquely providing design automation tools

319 views • 9 slides
DLX computer Electronic Computers M 1 RISC architectures RISC vs CISC (Reduced Instruction Set

DLX computer Electronic Computers M 1 RISC architectures RISC vs CISC (Reduced Instruction Set

DLX computer Electronic Computers M 1 RISC architectures RISC vs CISC (Reduced Instruction Set Computer vs Complex Instruction Set Computer In CISC architectures the 10% of the instructions are used in 90% of cases Waste of silicon

954 views • 48 slides
Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Which ISA

Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Which ISA

Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Which ISA runs in most cell phones and tablets? Letter Answer A ARM B x86 C MIPS D VLIW E CISC 2 Was the full x86 instruction set we have today

1.13k views • 69 slides
RISC Processors Chapter 14 S. Dandamudi Outline Introduction Itanium processor

RISC Processors Chapter 14 S. Dandamudi Outline Introduction Itanium processor

RISC Processors Chapter 14 S. Dandamudi Outline Introduction Itanium processor Architecture Evolution of CISC Addressing modes processors Instruction set RISC design principles Instruction-level parallelism

1.35k views • 70 slides
CISC vs. RISC x86 is the epitome of a Complex Instruction x86 or Set Computer Hundreds of

CISC vs. RISC x86 is the epitome of a Complex Instruction x86 or Set Computer Hundreds of

CISC vs. RISC x86 is the epitome of a Complex Instruction x86 or Set Computer Hundreds of instructions Oh No! Not Another Assembler F2XM1 Compute 2 x 1 Jonathan Misurda Computes the exponential value of 2 to the power of

417 views • 3 slides
Efficient Cryptography on the RISC-V Architecture Ko Stoffelen Tl;dr In this talk: Fast

Efficient Cryptography on the RISC-V Architecture Ko Stoffelen Tl;dr In this talk: Fast

Efficient Cryptography on the RISC-V Architecture Ko Stoffelen Tl;dr In this talk: Fast AES-128 assembly for RV32I Fast ChaCha20 assembly for RV32I Fast Keccak- f [1600] assembly for RV32I Fast arbitrary-precision integer

421 views • 19 slides
Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Goals for

Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Goals for

Instruction Set Architectures Part II: x86, RISC, and CISC Readings: 2.16-2.18 1 Goals for this Class Understand how CPUs run programs How do we express the computation the CPU? How does the CPU execute it? How does the

1.25k views • 99 slides
End-to-end formal ISA verification of RISC-V processors with riscv-formal Clifford Wolf About

End-to-end formal ISA verification of RISC-V processors with riscv-formal Clifford Wolf About

End-to-end formal ISA verification of RISC-V processors with riscv-formal Clifford Wolf About RISC-V RISC-V is an Open Instruction Set Architecture (ISA) Can be freely used for any purpose Many implementations are available from

677 views • 22 slides
Chapter 13 Reduced Instruction Set Computers Contents Instruction execution characteristics

Chapter 13 Reduced Instruction Set Computers Contents Instruction execution characteristics

Chapter 13 Reduced Instruction Set Computers Contents Instruction execution characteristics Use of a large register file Compiler-based register optimization Reduced instruction set architecture RISC pipelining MIPS

977 views • 58 slides
LECTURE 12 Out-of-order execution: Pentium Pro/II/III EXECUTING IA32/IA64 INSTRUCTIONS FAST

LECTURE 12 Out-of-order execution: Pentium Pro/II/III EXECUTING IA32/IA64 INSTRUCTIONS FAST

LECTURE 12 Out-of-order execution: Pentium Pro/II/III EXECUTING IA32/IA64 INSTRUCTIONS FAST Problem: Complex instruction set Solution: Break instructions up into RISC-like micro operations Lengthens decode stage; simplifies execute

1.3k views • 28 slides
SYSC3601 Microprocessor Systems Unit 13: RISC/CISC Comparison Topics/Reading 1. Review:

SYSC3601 Microprocessor Systems Unit 13: RISC/CISC Comparison Topics/Reading 1. Review:

SYSC3601 Microprocessor Systems Unit 13: RISC/CISC Comparison Topics/Reading 1. Review: 8086 Instruction Format and addressing modes. 68000 Instruction Format and addressing modes. 2. RISC vs. CISC comparison Motivation for

524 views • 24 slides
The Instruction Set Architecture Level Wolfgang Schreiner Research Institute for Symbolic

The Instruction Set Architecture Level Wolfgang Schreiner Research Institute for Symbolic

The Digital Logic Level The Instruction Set Architecture Level Wolfgang Schreiner Research Institute for Symbolic Computation (RISC-Linz) Johannes Kepler University Wolfgang.Schreiner@risc.uni-linz.ac.at

779 views • 52 slides
What makes a fast processor? 1. Instructions required per program ISA design: RISC vs. CISC

What makes a fast processor? 1. Instructions required per program ISA design: RISC vs. CISC

What makes a fast processor? 1. Instructions required per program ISA design: RISC vs. CISC 2. Memory bandwidth and latency Memory hierarchy Cache parameterisation 3. Instructions executed per second Internal CPU

260 views • 22 slides
Y86 encoding / SEQ part 1 1 last time instruction set (interface) v microarchitecture

Y86 encoding / SEQ part 1 1 last time instruction set (interface) v microarchitecture

Y86 encoding / SEQ part 1 1 last time instruction set (interface) v microarchitecture (implementation) RISC (simpler HW) v CISC (more fmexible ASM) Y86-64 ISA started Y86 encoding 3 Y86-64 instruction formats 9 0 rA rB OP q rA, rB 6 fn rA

1.2k views • 88 slides
The future of operating systems on RISC-V Alex Bradbury asb@lowrisc.org @asbradbury 4th

The future of operating systems on RISC-V Alex Bradbury asb@lowrisc.org @asbradbury 4th

The future of operating systems on RISC-V Alex Bradbury asb@lowrisc.org @asbradbury 4th March 2019 Structure of this talk Introduction to RISC-V RISC-V status Selected RISC-V topics RISC-V and open hardware: the future

733 views • 28 slides
PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine Installation and Setup 8:50am

PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine Installation and Setup 8:50am

Presentation Presentation Presentation Hands-On Presentation Hands-On Hands-On Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine

487 views • 7 slides
PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine Installation and Setup 8:50am

PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine Installation and Setup 8:50am

Presentation Presentation Presentation Hands-On Hands-On Presentation Hands-On Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine

355 views • 9 slides

More recommend