Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator - - PowerPoint PPT Presentation

▶
pydgin for risc v a fast and productive instruction set
SMART_READER_LITE
LIVE PREVIEW

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator - - PowerPoint PPT Presentation

Dec 06, 2023 783 likes •1.47k views

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems

slide-1
SLIDE 1

Cornell University Computer Systems Laboratory

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

Berkin Ilbeyi

In collaboration with Derek Lockhart (Google), and Christopher Batten

3rd RISC-V Workshop, Jan 2016 Cornell University Computer Systems Laboratory

slide-2
SLIDE 2

Motivation

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

1 / 16

Instruction-Set Architecture Software Hardware

slide-3
SLIDE 3

Motivation

1 / 16

Instruction-Set Simulator Software Hardware

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-4
SLIDE 4

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days)

Performance

Interpretive:

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-5
SLIDE 5

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours)

Performance

Interpretive: Typical DBT:

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-6
SLIDE 6

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance

Interpretive: Typical DBT: QEMU DBT:

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-7
SLIDE 7

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance Productivity

  • Develop
  • Extend
  • Instrument

Interpretive: Typical DBT: QEMU DBT:

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-8
SLIDE 8

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance Productivity

  • Develop
  • Extend
  • Instrument

Interpretive: Typical DBT: QEMU DBT:

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-9
SLIDE 9

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance Productivity

  • Develop
  • Extend
  • Instrument

Interpretive: Typical DBT: QEMU DBT:

Vendor Proprietary ISA

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-10
SLIDE 10

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance Productivity

  • Develop
  • Extend
  • Instrument

Interpretive: Typical DBT: QEMU DBT:

RISC-V Foundation RISC-V

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-11
SLIDE 11

Motivation

Instruction-Set Simulator Software Hardware

1-10 MIPS (1-10 days) 100s MIPS (1-3 hours) 1000 MIPS (0.5 hours)

Performance Productivity

  • Develop
  • Extend
  • Instrument

Interpretive: Typical DBT: QEMU DBT:

RISC-V Foundation RISC-V Specialized RISC-V Specialized RISC-V

1 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-12
SLIDE 12

2 / 16

Performance Productivity

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-13
SLIDE 13

Performance Productivity

Architectural Description Language Instruction Set Interpreter in C with DBT

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-14
SLIDE 14

Performance Productivity

Architectural Description Language Instruction Set Interpreter in C with DBT

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-15
SLIDE 15

Performance Productivity

Architectural Description Language Instruction Set Interpreter in C with DBT

[SimIt-ARM2006] [Wagstaff2013]

[Simit-ARM2006] J.D’Erricoand W.Qin. Constructing Portable Compiled Instruction-Set Simulators — An ADL-Driven Approach. DATE’06. [Wagstaff2013]

  • H. Wagstaff, M. Gould, B. Franke, and N.Topham. Early Partial Evaluation in a JIT-Compiled, Retargetable Instruction

Set Simulator Generated from a High-Level Architecture Description. DAC’13.

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-16
SLIDE 16

Performance Productivity

Instruction Set Interpreter in C with DBT Dynamic Language Interpreter in C with JIT Compiler

[SimIt-ARM2006] [Wagstaff2013]

Architectural Description Language

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-17
SLIDE 17

Performance Productivity

Instruction Set Interpreter in C with DBT Dynamic Language Interpreter in C with JIT Compiler

[SimIt-ARM2006] [Wagstaff2013]

Architectural Description Language

Key Insight: Similar productivity-performance challenges for building high-performance interpreters of dynamic languages. (e.g. JavaScript, Python)

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-18
SLIDE 18

Performance Productivity

Instruction Set Interpreter in C with DBT Dynamic Language Interpreter in C with JIT Compiler

[SimIt-ARM2006] [Wagstaff2013]

Architectural Description Language

Key Insight: Similar productivity-performance challenges for building high-performance interpreters of dynamic languages. (e.g. JavaScript, Python)

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-19
SLIDE 19

Performance Productivity

RPython Translation Toolchain

[SimIt-ARM2006] [Wagstaff2013]

Instruction Set Interpreter in C with DBT Dynamic-Language Interpreter in RPython Dynamic Language Interpreter in C with JIT Compiler Architectural Description Language

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-20
SLIDE 20

Performance Productivity

RPython Translation Toolchain

[SimIt-ARM2006] [Wagstaff2013]

Instruction Set Interpreter in C with DBT Dynamic-Language Interpreter in RPython Dynamic Language Interpreter in C with JIT Compiler Architectural Description Language Meta-Tracing JIT: makes JIT generation generic across languages

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-21
SLIDE 21

Performance Productivity

RPython Translation Toolchain Instruction Set Interpreter in C with DBT Architectural Description Language

Pydgin

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-22
SLIDE 22

Performance Productivity

RPython Translation Toolchain Instruction Set Interpreter in C with DBT Architectural Description Language

Pydgin

2 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

JIT ≈ DBT

slide-23
SLIDE 23

Pydgin Architecture Description Language

3 / 16

Architectural State Instruction Encoding Instruction Semantics

State Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-24
SLIDE 24

Pydgin Architecture Description Language

class State( object ): def __init__( self, memory, reset_addr=0x400 ): self.pc = reset_addr self.rf = RiscVRegisterFile() self.mem = memory # optional state if floating point is enabled if ENABLE_FP: self.fp = RiscVFPRegisterFile() self.fcsr = 0

4 / 16

Architectural State

State Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-25
SLIDE 25

Pydgin Architecture Description Language

encodings = [ # ... ['xori', 'xxxxxxxxxxxxxxxxx100xxxxx0010011'], ['ori', 'xxxxxxxxxxxxxxxxx110xxxxx0010011'], ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], ['sub', '0100000xxxxxxxxxx000xxxxx0110011'], ['sll', '0000000xxxxxxxxxx001xxxxx0110011'], # ... ]

5 / 16

Instruction Encoding

State Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-26
SLIDE 26

Pydgin Architecture Description Language

def execute_addi( s, inst ): s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.pc += 4 def execute_sw( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 def execute_beq( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4

6 / 16

Instruction Semantics

State Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-27
SLIDE 27

Pydgin Framework

7 / 16

def instruction_set_interpreter( memory ): state = State( memory ) while True: pc = state.fetch_pc() inst = memory[ pc ] # fetch execute = decode( inst ) # decode execute( state, inst ) # execute

State Pydgin Framework Encoding Semantics

Interpreter Loop

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-28
SLIDE 28

Pydgin Framework

7 / 16 State Pydgin Framework Debug on Python Interpreter Encoding Semantics

def instruction_set_interpreter( memory ): state = State( memory ) while True: pc = state.fetch_pc() inst = memory[ pc ] # fetch execute = decode( inst ) # decode execute( state, inst ) # execute

Interpreter Loop

100 KIPS

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-29
SLIDE 29

The RPython Translation Toolchain

8 / 16

RPython Source Type Inference Opmizaon Code Generaon Compilaon Compiled Interpreter

State Pydgin Framework RPython Translation Toolchain Debug on Python Interpreter Encoding Semantics

100 KIPS

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-30
SLIDE 30

The RPython Translation Toolchain

8 / 16

RPython Source Type Inference Opmizaon Code Generaon Compilaon Compiled Interpreter

State Pydgin Framework RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Encoding Semantics

100 KIPS 10 MIPS

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-31
SLIDE 31

The RPython Translation Toolchain

8 / 16

RPython Source Type Inference Opmizaon Code Generaon Compilaon JIT Generator Compiled Interpreter with JIT

State Pydgin Framework RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Encoding Semantics

100 KIPS 10 MIPS

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-32
SLIDE 32

The RPython Translation Toolchain

8 / 16

RPython Source Type Inference Opmizaon Code Generaon Compilaon JIT Generator Compiled Interpreter with JIT

State Pydgin Framework RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

100 KIPS 10 MIPS <10 MIPS

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-33
SLIDE 33

JIT Annotations and Optimizations

9 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

100 KIPS 10 MIPS 100+ MIPS

Additional RPython JIT hints:

+ Elidable Instruction Fetch + Elidable Decode + Constant Promotion of PC and Memory + Word-Based Target Memory + Loop Unrolling in Instruction Semantics + Virtualizable PC and Statistics + Increased Trace Limit

SPECINT2006 on ARM

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-34
SLIDE 34

JIT Annotations and Optimizations

9 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

100 KIPS 10 MIPS 100+ MIPS

Additional RPython JIT hints:

+ Elidable Instruction Fetch + Elidable Decode + Constant Promotion of PC and Memory + Word-Based Target Memory + Loop Unrolling in Instruction Semantics + Virtualizable PC and Statistics + Increased Trace Limit

SPECINT2006 on ARM 23X improvement

  • ver no annotations

Please see our ISPASS paper for more details!

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-35
SLIDE 35

Pydgin Performance

10 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-36
SLIDE 36

Pydgin Performance

10 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-37
SLIDE 37

Pydgin Performance

10 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-38
SLIDE 38

Pydgin Performance

10 / 16

Spike is an interpretive simulator with some advanced DBT features:

  • Caching decoded

instructions

  • PC-indexed dispatch

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-39
SLIDE 39

Pydgin Performance

10 / 16

Spike is an interpretive simulator with some advanced DBT features:

  • Caching decoded

instructions

  • PC-indexed dispatch

RISC-V QEMU port was out-

  • f-date at the time of our

development

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-40
SLIDE 40

Pydgin Productivity

11 / 16

RISC-V encourages ISA extensions.

RISC-V Foundation RISC-V Specialized RISC-V Specialized RISC-V

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-41
SLIDE 41

Pydgin Productivity

11 / 16

RISC-V encourages ISA extensions.

  • Productive Development
  • Productive Extensibility
  • Productive Instrumentation

RISC-V Foundation RISC-V Specialized RISC-V Specialized RISC-V

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-42
SLIDE 42

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-43
SLIDE 43

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-44
SLIDE 44

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-45
SLIDE 45

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-46
SLIDE 46

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-47
SLIDE 47

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-48
SLIDE 48

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-49
SLIDE 49

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-50
SLIDE 50

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-51
SLIDE 51

Pydgin RISC-V Development

12 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

100+ MIPS simulator after 9 days of development!

slide-52
SLIDE 52

Pydgin Extensibility

encodings = [ # ... ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], # ... ['custom2', 'xxxxxxxxxxxxxxxxx000xxxxx1011011'], # ... ] # greatest common divisor semantics def execute_gcd( s, inst ):

13 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-53
SLIDE 53

Pydgin Extensibility

encodings = [ # ... ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], # ... ['gcd', 'xxxxxxxxxxxxxxxxx000xxxxx1011011'], # ... ] # greatest common divisor semantics def execute_gcd( s, inst ):

13 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-54
SLIDE 54

Pydgin Extensibility

encodings = [ # ... ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], # ... ['gcd', 'xxxxxxxxxxxxxxxxx000xxxxx1011011'], # ... ] # greatest common divisor semantics def execute_gcd( s, inst ): a, b = s.rf[inst.rs1], s.rf[inst.rs2] while b: a, b = b, a%b s.rf[inst.rd] = a s.pc += 4

13 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-55
SLIDE 55

Pydgin Instrumentation

# count number of adds def execute_addi( s, inst ): s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.pc += 4 # count misaligned stores def execute_sw( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 # record and count all executed loops def execute_beq( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4

14 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-56
SLIDE 56

Pydgin Instrumentation

# count number of adds def execute_addi( s, inst ): s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.num_adds += 1 s.pc += 4 # count misaligned stores def execute_sw( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 # record and count all executed loops def execute_beq( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4

14 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-57
SLIDE 57

Pydgin Instrumentation

# count number of adds def execute_addi( s, inst ): s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.num_adds += 1 s.pc += 4 # count misaligned stores def execute_sw( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) if addr % 4 != 0: s.num_misaligned += 1 s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 # record and count all executed loops def execute_beq( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4

14 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-58
SLIDE 58

Pydgin Instrumentation

# count number of adds def execute_addi( s, inst ): s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.num_adds += 1 s.pc += 4 # count misaligned stores def execute_sw( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) if addr % 4 != 0: s.num_misaligned += 1 s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 # record and count all executed loops def execute_beq( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]:

  • ld_pc = s.pc

s.pc = trim_xlen( s.pc + inst.sb_imm ) if s.pc <= old_pc: s.loops[(s.pc,

  • ld_pc)]

+= 1 else: s.pc += 4

14 / 16 State Pydgin Framework + JIT Annot. RPython Translation Toolchain Debug on Python Interpreter Pydgin Interpretive Simulator Pydgin DBT Simulator Encoding Semantics

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-59
SLIDE 59

Pydgin in Our Research Group

  • Statistics for software-defined regions

15 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-60
SLIDE 60

Pydgin in Our Research Group

  • Statistics for software-defined regions
  • Data-structure specialization experimentation

15 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-61
SLIDE 61

Pydgin in Our Research Group

  • Statistics for software-defined regions
  • Data-structure specialization experimentation
  • Control- and memory-divergence for SIMD

15 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-62
SLIDE 62

Pydgin in Our Research Group

  • Statistics for software-defined regions
  • Data-structure specialization experimentation
  • Control- and memory-divergence for SIMD
  • Basic Block Vector generation for SimPoint

15 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-63
SLIDE 63

Pydgin in Our Research Group

  • Statistics for software-defined regions
  • Data-structure specialization experimentation
  • Control- and memory-divergence for SIMD
  • Basic Block Vector generation for SimPoint
  • Analysis of JIT-enabled dynamic language interpreters

15 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-64
SLIDE 64

Conclusions

Pydgin leverages the RPython translation toolchain into high- performance, DBT Instruction Set Simulator.

16 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-65
SLIDE 65

Conclusions

Pydgin leverages the RPython translation toolchain into high- performance, DBT Instruction Set Simulator. Pydgin provides a succinct architecture description language within Python to give users a productive development, extension, and instrumentation experience.

16 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-66
SLIDE 66

Conclusions

Pydgin leverages the RPython translation toolchain into high- performance, DBT Instruction Set Simulator. Pydgin provides a succinct architecture description language within Python to give users a productive development, extension, and instrumentation experience. Current State: RV64IMAFD (RV64G) Bare-Metal on 64-bit host

16 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

slide-67
SLIDE 67

Conclusions

Pydgin leverages the RPython translation toolchain into high- performance, DBT Instruction Set Simulator. Pydgin provides a succinct architecture description language within Python to give users a productive development, extension, and instrumentation experience. Current State: RV64IMAFD (RV64G) Bare-Metal on 64-bit host

https://github.com/cornell-brg/pydgin

Thank you to our sponsors for their support: NSF, DARPA, and donations from Intel Corporation and Synopsys, Inc.

Pydgin

16 / 16

Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator