Preallocating Resources for Distributed Memory based FPGA Debug - PowerPoint PPT Presentation

Feb 09, 2024 •311 likes •618 views

Preallocating Resources for Distributed Memory based FPGA Debug Robert Hale & Brad Hutchings FPGA Debug - Logic Analyzer 1. External? 2. Internal? Time Resources Xilinx Internal Logic Analyzer (ILA) FPGA with 94% of LUT

Preallocating Resources for Distributed Memory based FPGA Debug Robert Hale & Brad Hutchings
FPGA Debug - Logic Analyzer 1. External? 2. Internal? ● Time ● Resources
Xilinx Internal Logic Analyzer (ILA)
FPGA with 94% of LUT resources utilized: Xilinx ILA: Where will the embedded logic analyzer fit?
Can we debug at all?
Xilinx Shift Register LUT (SRL)
Distributed Memory (DIME) Debug
Process JTAG
4-bit Counter Output
DIME Debug - Research Questions 1. Can we enable internal debug when the device is 90%+ utilized? 2. How will DIME trace buffers impact the user circuit (timing)? 3.What is the ideal organization of DIME buffers on the device?
How do we organize those LUTs?
DIME Preallocation - Research Questions 1. Will this hurt the performance of the user circuit? 2. Will this improve performance of the combined DIME + user circuit?
Benchmarks LC3 Sudoku RPulseG RNG uFIFO
Preallocation - Affect User Design? ● Implementation: No impact ● Timing: Max 0.1ns
Preallocation - Affect DIME Debug? LC3 90% LC3 90% (with preallocation)
Results RPulseG Sudoku uFIFO RNG
LC3 Can we lengthen DIME trace buffers? RPulseG Sudoku uFIFO RNG
Conclusion ● DIME debug: 90%+ utilized designs ● Preallocating FPGA resources for DIME debug: ○ Almost no impact on original design ○ Reduce timing penalty (up to 2ns) ○ Increase trace buffer count (up to ~3x) ● DIME trace buffers can be lengthened
Thank you Research supported by Xilinx Research Labs Robert Hale robert.hale@byu.edu
<This Page Intentionally Left Blank>
Contributions ● Pros/cons of preallocating LUTs for DIME trace buffers ● 5 unique (duplication-based) benchmarks ● Extending DIME trace buffers to 256 bits
Process
Experiments <describe experiments> <diagram?>
DIME Debug - Research Questions 1. How many user signals can I access? 2. How big are the trace buffers? 3. What is the impact to the user circuit (timing)?
Pinterest FPGA:
LC3 Can we lengthen DIME trace buffers? RPulseG Sudoku uFIFO RNG
Real FPGA: Where will the embedded logic analyzer fit?
Experiments Will preallocating resources improve the distributed-memory debug process? ● Timing? ● Debug bits?

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