Power System Driven Hardware in the y Loop Simulations at Florida State University's Center for Advanced University s Center for Advanced Power System Michael “Mischa” Steurer Power Systems Research Group Leader at FSU-CAPS y p Email: steurer@caps.fsu.edu, phone: 850-644-1629 TCIPG Seminar U i University of Illinois it f Illi i Dec 2 2011, Champaign, IL
Outline • Overview of CAPS • Overview of CAPS • Hardware in the Loop (HIL) Concepts and Challenges Challenges – Real Time Simulators – Interfaces Interfaces – Examples • CAPS Facility Expansions y p • Concluding Remarks 2 12/2/2011 TCIPG_Seminar_Steurer
FSU Center for Advanced Power Systems Research Focus • Established at Florida State University in 2000 under a grant from the Office of • Electric Power Systems Naval Research • Advanced Modeling and Simulation • Advanced Control Systems • Advanced Control Systems • L Lead Member of ONR Electric Ship R&D d M b f ONR El t i Shi R&D • Power Electronics Integration and Controls Consortium • Thermal Management • Focus on research and education related • High Temperature Superconductivity to application of new technologies to • Electrical Insulation/Dielectrics • Electrical Insulation/Dielectrics electric power systems • ~$8 million annual research funding from –44,000 square feet laboratories and ONR, DOE, Industry offices located in Innovation Park, , • DOD cleared Facility at Secret Level DOD cleared Facility at Secret Level Tallahassee; over $25 million specialized power and energy capabilities funded by ONR, DOE –Employs approx. 100, including E l 100 i l di –46 scientists, engineers and technicians, post-doc.’s and supporting staff, –7 FAMU-FSU College of Engineering faculty 7 FAMU FSU College of Engineering faculty –44 Students 3 12/2/2011 TCIPG_Seminar_Steurer
CAPS Organization 4 12/2/2011 TCIPG_Seminar_Steurer
Major Collaborative Research and Education Initiatives in Energy with CAPS Participation – Florida State University – Massachusetts Institute of Technology – Mississippi State University – Purdue University – University of South Carolina – U.S. Naval Academy and Naval Post http://www.esrdc.com/ Graduate School – University of Texas at Austin http://www.floridaenergy.ufl.edu/ Future Renewable Electric Energy Delivery and Management (FREEDM) Systems Engineering Research Center (ERC) http://www.freedm.ncsu.edu/ The Sunshine State Solar Grid Initiative (SUNGRIN) 5 12/2/2011
Early Stage Prototype Testing Needs Test under different (grid) conditions Modification of configuration(s) Repeatability: Capability for exact reproduction of testing conditions Drawbacks of conventional testing Expenses in construction Time intensive Facilities for high power are rare Extreme scenarios endanger equipment Possible solution Power HIL 6 12/2/2011 TCIPG_Seminar_Steurer
Controller Hardware in Loop (CHIL) and Power Hardware in loop (PHIL) Simulator • Controller HIL Simulation D/A D/A A/D A/D – Controller under test – Low level transmitting signals (+/-15V, mA) A/D D/A – A/D and D/A converters are adequate for q C Controller t ll the interface under Test Simulator Simulator D/A A/D Power HIL Simulation – Power device (load, sink) under test ( , ) Power Interface Power Interface – High level transmitting signals (kV, kA, MW) – Power amplifiers required for interface A/D D/A Power Device Power Device under Test 7 12/2/2011 TCIPG_Seminar_Steurer
FSU-CAPS Power Testing Facility 5 MW MVDC facility (future) 5 MW MVAC and LVDC facility Offices and labs 8 12/2/2011 TCIPG_Seminar_Steurer
FSU-CAPS Power Testing Facility 12.5 kV and 4.16 kV transformers 12.5 kV and 4.16 kV switchgear 2 x 2.5/5 MW dynamometers 2 x 8 MVA / 5 MW variable speed drives 9 12/2/2011 TCIPG_Seminar_Steurer
5 MW Electrical PHIL Facility at FSU-CAPS Real Time Simulator RTDS 6.25 MVA / 5 MW Variable Voltage 4.16 kV / 7 MVA Source (VVS) Converter “Amplifier“ utility bus Voltage / current reference / feedback f S = 10 kHz effective f = 10 kHz effective from / to RTDS from / to RTDS Bandwidth 1.2 kHz 0…1.15 kV / 2.5 MW experimental DC 0….4.16 (8.2) kV / 6.25 MVA bus (ungrounded) experimental AC bus (ungrounded) 0-480 V / 1.5 MVA experimental AC bus (ungrounded) 10 12/2/2011 TCIPG_Seminar_Steurer
CAPS Facility Power System Simulation, Control, and Information Capabilities Systems Development, Test, Evaluation, and Power and Energy Educational Kiosk Demonstration Facility CoE Solar Array EMS / SCADA workstation PI workstation CAPS Solar Array Commercial • 7.5 MVA, 4.16kV test and evaluation facility digital relays CAPS (SEL, Beckwith) Network – 5 MW variable voltage / variable frequency OSI PI Shadow Server converter Firewall FSU Campus and Innovation Park Commercial Commercial Energy Systems and Metering process information – 5 MW dynamometer systems (OSI PI) OSI PI Server EMS Server – High-speed machine capability, to 24,000 RPM Control Commercial EMS Network EMS / SCADA Collector Rockwell Controllogix and SCADA systems (Areva) – Switchgear and transformers g MODBUS Relays Hard I/O MODBUS DNP3 • Real-time Digital Simulator (RTDS) Hard I/O MODBUS SERVER Power System GTNET GTNET Down to <2 μ Sec time step in real-time – RTDS • Integrated Hardware-in-the-Loop (HIL) testbed 5 MW testbed + RTDS testbed 5 MW testbed + RTDS Hi-fidelity real-time power • Low power dynamometers and converters system simulation • AC Loss and Quench Stability Lab g B1 • Cryo-cooled systems lab y y 12.47 kV Future B2 B3 B4 4.16 kV Exp. Bus (Port) Actual power p Future Future Future T1 and control Feed Feed SP2 SP4 SP6 SP8 SP10 SP12 SP14 SP16 B15 • Cryo-dielectrics Lab S10 4.16 kV systems S4 S5 B11 B13 interacting “in- S8 T9.1 T9.2 B12 B5 B6 the-loop” with C4 T5 – With high voltage test capability T6 T7 ~ ~ hi-fidelity C1 C2 = = ~ ~ ~ 450 VAC simulation = = = = = ~ ~ = = = DC Bus ~ ~ ~ T10.1 T10.2 500-1150 VDC 1.5MW @ 600VDC 2.8MW @ 1150VDC B14 Additions and Enhancements in Progress Additions and Enhancements in Progress 5 MW VVF AC Bus 5 MW M1 M2 SS1 SS3 SS5 SS7 SS9 SS11 SS13 SS15 Future Max 4.16 kV Exp. Bus (Starboard) 2.5 MW 2.5 MW • MVDC test capability to +/- 24 kV 11 12/2/2011 TCIPG_Seminar_Steurer
Real-Time Computer Simulation • What does it mean? – Real-Time simulation means producing the true system behavior p g y or dynamics through simulation at the same rate as it happens in an actual physical system • Main Characteristics Main Characteristics – Simulation must be completed within the specified time-step – Should be able to interface with physical hardware 12 12/2/2011 TCIPG_Seminar_Steurer
Transient Network Simulators Digital versus Analog • Flexibility • User friendliness • Maintenance • Maintenance • Digital interfaces • Model portability Model portability Courtesy BPA 13 12/2/2011 TCIPG_Seminar_Steurer
Power Systems Simulations at CAPS REAL-TIME – using RTDS • Large-scale electromagnetic transient simulator • EMTP type simulation covers load-flow, yp harmonic, dynamic, and transient regime • 111,200 MFLOPS; 14 “racks”, parallel processing • Real-time simulation, with time steps down to <2 s s. • Real-time simulation of 756 electrical nodes, plus hundreds of control and other simulation blocks RT simulator lab at CAPS • Extensive digital and analog I/O for interfacing Example : IEEE 30-bus System Example : IEEE 30 bus System hardware to simulation ( >2500 analog, >200 digital). • 5 racks, dt=65 μ s Can connect in real-time to any electrical node within the • 6 machines incl. governor & v-regulator simulation. • 36 transmission lines • MODBUS TCP, DNP 3.0 and IEC 61850 • 70 breakers i t interfaces also available. f l il bl • Capability for remote access over VPN link Other simulation tools in-use at CAPS: • PSS/E PSCAD/EMTDC MATLAB/Simulink PSS/E, PSCAD/EMTDC, MATLAB/Simulink, ATP, PSPICE, ANSYS, DSPACE, OPAL-RT 14 12/2/2011 TCIPG_Seminar_Steurer
OPAL-RT Real-Time Simulator OS-RedHat Linux OS-Windows Key Features- 1. General purpose CPU based Host Host 2 Simulink based model 2. Simulink based model development 3. MATLAB, C/C++, FORTRAN code can be simulated 4 Supports multi physics domain 4. Supports multi physics-domain simulations Xilinx Simulink Simulink Coded Coded CPU Blockset 5. Reconfigurable FPGA based I/O Model Model Model Model Model 6. Supports user developed models 16 DO 16 DI ESS Sh.Mem. partan 3) Carrier (op5210) Hardware EMTP-RV INTERFACE 16 AO 16 AI software JMAG-RT RT-EVENTS ARTEMiS CPU Carrier w (op511x) PCI EXPRE Other Third party s External H FPGA (S Blocksets 16 AO 16 AI XILINX XSG SimPower Stateflow Stateflow Stateflow Stateflow Stateflow Carrier w (op511x) Systems Toolboxes PCI Express 16 DO 16 DI Carrier (op5210) ( p ) RTW Stateflow Stateflow FastCom Other Targets Target RT-LAB , QNX, LINUX, XSG, ORCHESTRA 15 12/2/2011 TCIPG_Seminar_Steurer
Examples of Controller Hardware in the Loop (CHIL) Simulation Projects Simulator D/A D/A A/D A/D A/D D/A Controller Controller under Test 16 12/2/2011 TCIPG_Seminar_Steurer
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