Power Manager Chenyang Lu CSE 467S 1 HW vs. SW? Software - PDF document

Power Manager Chenyang Lu CSE 467S 1 HW vs. SW? • Software (OS-based) power manager dominates due to flexibility • Hardware and software co-design • Software implements policy • Hardware implements power change mechanisms • Need standard interfaces to deal with hardware diversity • Different vendors • Different devices: processor, sensor, controller … Chenyang Lu CSE 467S 2

Advanced Configuration and Power Interface (ACPI) Open standard for power management services. applications power OS kernel management device drivers ACPI BIOS Hardware platform devices, processor, chipset Chenyang Lu CSE 467S 3 System States Chenyang Lu CSE 467S 4

ACPI Global Power States • Used as contracts between hw and OS vendors • G3: mechanical off – no power consumption • G2: soft off – restore requires full OS reboot • G1: sleeping state • S1: low wake-up latency with no loss of context • S2: low latency with loss of CPU/cache state • S3: low latency with loss of all state except memory • S4: lowest-power state with all devices off • G0: working state Chenyang Lu CSE 467S 5 Device Power States • Device power state is invisible to the user • Some device may be inactive when the system is in working state • Each device may be controlled by a separate PM policy Chenyang Lu CSE 467S 6

Reduce power in working state Chenyang Lu CSE 467S 7 Holistic View of Power Consumption • Instruction execution (CPU) • Cache (instruction, data) • Main memory • Other: non-volatile memory, display, network interface, I/O devices Chenyang Lu CSE 467S 8

Sources of energy consumption • Relative energy per operation (Catthoor et al): • memory transfer: 33 • external I/O: 10 • SRAM write: 9 • SRAM read: 4.4 • multiply: 3.6 • add: 1 Chenyang Lu CSE 467S 9 Optimize Memory System • Different instructions � Different energy consumption • Energy drain: register << cache (SRAM) << memory (DRAM) → Most energy reduction comes from optimizing memory system Chenyang Lu CSE 467S 10

Cache behavior is important • Energy consumption has a sweet spot as cache size changes: • cache too small: burning energy on external memory accesses; • cache too large: cache itself burns too much power. Chenyang Lu CSE 467S 11 Impacts of Cache Size Chenyang Lu CSE 467S 12

Optimizations • Reduce memory footprint • Reduce code size • Analyze footprint to find right size • Stack, heap… • Find correct cache size • Analyze cache behavior (size of working set) • Minimize memory and cache access • Use registers efficiently � less cache access • Identify and eliminate cache conflicts � less memory access • Better performance � More idle time! Chenyang Lu CSE 467S 13 Wireless Sensor Networks A Quick Overview • sensors + microprocessor + wireless Berkeley Smart Dust Chenyang Lu CSE 467S 14

Hardware Technology Chenyang Lu CSE 467S 15 The Hardware Challenge • Miniature hardware devices must be manufactured economically in large numbers • Microprocessors • MEMS sensors/actuators • Wireless communication 1 mm 2 1 nm 2 5’’X3’’ 1’’X1’’ Chenyang Lu CSE 467S 16

MICA Motes • Radio Communication: 40 Kbps max • Commercial-off-the-shelf components 1’’X1’’ Chenyang Lu CSE 467S 17 Smart Dust • Current: 5 mm; in ten years: 1 mm � float in the air! • Radio? • Nowhere to put antenna! • Require complex circuits � energy-inefficient Chenyang Lu CSE 467S 18

Passive Optical Communication Top View of the Interrogator Quarter-wave Filter Plate Polarizing Beamsplitter Lens CCD Camera 0.25% reflectance on each surface Frequency-Doubled Beam 45 o mirror YAG Green Laser Expander K. Pister et. al., http://robotics.eecs.berkeley.edu/~pister/SmartDust/presentations/MEMSPIJan00.ppt Chenyang Lu CSE 467S 19 Optical Communication • Pros • Space multiplexing • Passive optical communication: energy-free on dusts! • Cons • Require line of sight • Much more challenging for active multi-hop communication • aiming control Chenyang Lu CSE 467S 20

Amorphous Computing • Computers produced by bio engineering • Cells as logic gates • Basic inverter: Concentration of protein Z is inversely proportional to concentration of protein A. • NAND gate: Production of protein Z is inhibited by presence of proteins A and B. Chenyang Lu CSE 467S 21 Nano-scale Computing • DNA manipulation can organize cells into engineered patterns • The foundation for construction of complex sub-nano-scale extra-cellular circuits: • Biological system – machine shop • Proteins – machine tools • DNA – control tapes • Circuits are fabricated in large numbers by cheap biological processes • Truly ubiquitous ! Smart paint, fabric … Chenyang Lu CSE 467S 22

Great Duck Island Habitat Monitoring Usage patterns of burrows • Burrow and environmental • changes Differences between • nesting areas and others Chenyang Lu CSE 467S 23 Chenyang Lu CSE 467S 24

Great Duck Island Requirements Longevity: 9-month season • Super-low Power budget • Need extreme power management! • Non-intrusive • Management from remote • System health monitoring • Retasking/reconfiguration through wireless • Maté, Agilla (from MobiLab) • Timing requirements (non-real-time) • 5-10 min: entry/leave • 2-4 hr: environmental differential • Chenyang Lu CSE 467S 25 Great Duck Island Tiered Architecture http://www.greatduckisland.net Chenyang Lu CSE 467S 26

Mote and TinyOS Chenyang Lu CSE 467S 27 Hardware Constraints • Severe constraints in power, size, and cost translated to: • Slow CPU • Short-distance, low-bandwidth radio • Small memory • Limited hardware parallelisms • CPU hit by many interrupts! • Support sleep mode in hw components Chenyang Lu CSE 467S 28

Mote • CPU: 4 MHz, 8 bit, ATMEL • NO kernel/user protection • Raw peripherals � a lot work for CPU: • Collect data from sensors • Process every bit to/from radio • Arbitrate bus • Radio: 900 Hz • Rene: 19.2 kbps • Mica: 40 kbps (max), up to 1,000 feet (power adjustable) • No byte level processing • Memory: Harvard Architecture • Rene: 512 B data; 8K code • Mica: 4 KB data; 128 KB code • Two AA battery • 3 days of continuous active operation • Sleep modes: idle/power-down/power-save Chenyang Lu CSE 467S 29 Software Challenges • Small memory footprint • Efficient in power and computation • Lack hardware parallelism � OS provides concurrency-intensive operation • Real-time • Diversity in applications and design � • Efficient modularity • Reconfigurable hardware • Software & hardware codesign Chenyang Lu CSE 467S 30

How about a traditional embedded OS? • Big! • Multi-threaded architecture • Large number of threads � large memory • Context switch overhead • I/O model • Blocking I/O (stop and go): waste memory on blocked threads • Polling (busy-wait): waste CPU cycles and power • Protection between applications and kernel • Overhead for crossing kernel/user boundary & interrupt handling • Pros • Clean & simple programming model • Priority-based scheduling support • Robust (protect kernel) Chenyang Lu CSE 467S 31 Real time operating systems Name Code Size Target CPU pOSEK 2K Microcontrollers pSOSystem PII->ARM Thumb VxWorks 286K Pentium -> Strong ARM QNX Nutrino >100K Pentium II -> NEC QNX RealTime 100K Pentium II -> SH4 OS-9 Pentium -> SH4 Chorus OS 10K Pentium -> Strong ARM ARIEL 19K SH2, ARM Thumb Creem 560 bytes ATMEL 8051 • QNX context switch = 2400 cycles on x86 • pOSEK context switch > 40 µs • Creem -> no preemption Chenyang Lu CSE 467S 32

TinyOS Solutions • Support concurrency: event-driven architecture • Modularity: application = scheduler + graph of components • Compiled into one executable • Efficiency: Get done quickly and sleep • Event = function calls • Less context switch: FIFO/non-preemptable scheduling • No kernel/application boundary Main (includes Scheduler) Application (User Components) Actuating Sensing Communication Communication Hardware Abstractions Modified from D. Culler et. Al., TinyOS boot camp presentation, Feb 2001 Chenyang Lu CSE 467S 33 TinyOS component model • Component has: Messaging Component • Frame (memory) Internal State • Tasks: thread (computation) Internal Tasks • Interface: • Command • Event Commands Events • Frame: static storage model – compile-time allocation • Command and events = function calls • Clean (hw-like) interface • No shared memory or global variables • Replace hw with sw and vice versa Chenyang Lu CSE 467S 34