Paul Scherrer Institut Pixel Detector for the Protein Crystallography Beamline at the SLS PSI Ch. Brönnimann 1 , E. Eikenberry 1 , S. Kohout 1 , B. Schmitt 1 , C. Schulze 1 , R. Baur 2 and R.Horisberger 2 1 Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen-PSI 2 CMS-Project, Paul Scherrer Institut, CH-5232 Villigen-PSI University of Bonn P. Fischer 3 , S. Florin 3 and M. Lindner 3 3 Physikalisches Institut der Universität Bonn, Nussallee 12 D-53115 Bonn Ch. Brönnimann, SLS
Paul Scherrer Institut Data collection in protein crystallography X-ray Detector Spot size: - Beam divergence - Mosaicity of the crystal - Distance sample-detector θ - Point spread function of detector Diffraction pattern Diffracted beam Crystal rotation - 30-180 degree for complete data set - Currently: Discrete rotation, integration over certain rotation angle - Future: Continuous rotation, integration determined by detector frame rate ( Fine phi slicing ) Resolution: ⋅ θ = λ 2 d 2 d sin( sin( ) ) Crystallized o λ θ Protein For d=1A and =1A, =60 Beam Beam Diffraction data Energy: 5-17.5 keV - reflect crystal symmetry group 13 Intensity: ~10 /s - orientation of the crystal-> orientation matrix 4 Focal spot size: Adjustable to - High dynamic range: >10 between strong and weak reflections 2 µ 25 x 15 m - Intensities need to be determined accurately (1%) Divergency:150 µrad x 28 µrad - Determination of amplitudes and phases leads (FWHM) to electron density maps Detector requirements: 2 - Large area (40 x 40 cm ) and/or large number of pixels - Detect a high number of reflection orders (>500) - Accurate determination of integrated intensities - Wide dynamic range (>16 bit, i.e. single photon counting detector) - Fast readout (<0.1s) Ch. Brönnimann, SLS
Paul Scherrer Institut Pixel Detectors: Principle X-rays Si pn-junction Al 3.6 eV to create p+ - E drift V bias 1 eh-pair + n+ n++ Detector 0.2 mm X-rays Pixel Sensor 0.2 mm 0.3 mm Sensor Chip Pixel Read-out Chip Bump Bonds Radiation hard Pixel electronics Ext/Comp Treshold Clock correction - 15 bit RBI Φ 12 Global Comp SR + Clock Tresh Bump counter RBO Gen Pad CS Amp Ext Enable/ Clock Reset Disable 1.7fF Cal Digital Block Analog Block Ch. Brönnimann, SLS
Paul Scherrer Institut The SLS Pixel Detector & Size: 40 x 40 cm 2 (0.16m 2 ) & 2000 x 2000 pixels & Pixel size: 200 x 200 µ m 2 & Modular detector -> dead area ~6% & High frame rate: >10Hz & High duty cycle: <6% (T ro ~6ms) & In operation: 1.8.2001 (1000x1000) Base plate (water cooled) Bank with 5 modules Modules with 16 chips Ch. Brönnimann, SLS
Paul Scherrer Institut SLS Pixel Module Sensor Wire bonds Read-out chips High density flexible capton interconnect Base plate Al support Module Control Board MCB Cable Ch. Brönnimann, SLS
Paul Scherrer Institut Module Geometry 36.5 2 4 6 8 10 12 14 16 35.4 0.11 18.25 1 3 5 7 9 11 13 15 34 9.82 79.6 Sensitive Area 0.18 81.0 Horizontal Vertical Total Pixel size 0.2 0.2 mm 0.04 mm^2 Chip Nr of pixels 48 85 4080 Chip size 9.82 18.25 mm 179.215 mm^2 Sensor Nr of Pixels 398 170 67660 Nr of double pixels 14 170 2380 Sensor active area 79.6 34 2706.4 Module outside dim 81 36.6 mm 2964.6 mm^2 Sensor Pixels Readout chip Readout chip 110 200 Readout chip Readout chip 125 275 140 Chip Pixels Ch. Brönnimann, SLS
Paul Scherrer Institut Read-out electronics Main parameters ! Low noise analog block (ENC tot < 100 e-) ! Shaping time t sh = 100 ns -> 1MHz ! Radiation tolerant ! power consumption <100 µ W/Pixel ! Robust comparator ! Individual threshold adjustment ! Low overall threshold variation ( σ < 100e-) ! 15 bit pseudo random counter ! Large size (20 x 10 mm 2 ) Prototypes Name Size Pixel Architecture Chip Subm. Receiv. Architecture SLS01 8x2 array Analog, comparator, - Dez 98 April 99 counter SLS02 22 x 30 Analog, comparator!, Indiv. May 99 Nov 99 counter, trimbits Coloumn architectur SLS03 1 x 90 As SLS02, final length - Aug 99 Mar 00 column SLS04 22 x 30 As SLS02 but with As SLS02 Dez 99 Exp May 00 correct comparator SLS05 30 x 30 As SLS04, improved Indiv. Pixel Feb 00 Exp July 00 trimbit Architecture mechanism (Yield tolerant design) SLS06 48 x 85 As SLS05 As SLS05 Exp Oct 00 Exp Feb 01 (Final chip) Ch. Brönnimann, SLS
Paul Scherrer Institut Pixel Layout Designed in radiation hard DMILL technology (R. Baur, Ch. Brönnimann) Size: 200 x 200 µ m 2 15 bit semi-static pseudo random counter+ Bump Pad control logic Low noise preamp (folded cascode) Shaper Threshold trimming (3 Bits) AC-coupled comparator Size 200 x 200 µ m Ch. Brönnimann, SLS
Paul Scherrer Institut SLS02 Architecture Column1 Icomp Column22 Pixel Vcal 10f 20f Pixel 30 + 1.5f LS 200f 100f Comp Pr 15Bit Sh 200f Analog Counter Pad Mode Dis comp Phi1 Clockgen clk Phi2 DIS Mode previous ds_shift ds_shift ds_shift ds_shift ds_shift ds_shift next Pixel1 Bit1 Bit2 Bit3 Bit13 Bit14 Bit15 Xor Xor CLK OUT CLK Mode Mode Column Column Column Control Control Control & & > & & > & & > Shift Shift Shift Clock Clock Clock Gen Gen Gen In DOUT CLK DIS FF ChipControl Shift Shift Clock gen TCL OUT TBI TBO Ch. Brönnimann, SLS
Paul Scherrer Institut Pixel: Preamp-Shaper I =I +I comp c trim Vcal 10f 20f 1.7f Comp Shaper Preamp 80f 200f 100f FB FC=folded cascode SF=source follower FB=Feedback FC SF Shaper Preamp t ~30ns peak t ~60ns shape Ch. Brönnimann, SLS
Paul Scherrer Institut SLS02 Analog Part Results Analog out signal Calibration signal 100ns/div, Ch1: 100mV/div, Ch2: 50mV/div ! Noise measurements (without detector): ENC ~50e- (P=75 µ W/pixel, t sh = 100 ns) ! Amplification: ~60mV/1000e- Analog 450 400 Output y = 0.0564x + 18.14 350 ! Linearity limit: ~6000e (21keV) [mV] 300 250 200 150 100 50 0 0 1000 2000 3000 4000 5000 6000 7000 Noise depence on feedback resistors settings Signal charge VRF\VRFS -700 -600 -500 -400 -300 -200 300 96 71 63 74 45 70 200 95 69 61 56 50 77 100 96 82 67 75 64 78 0 120 98 100 75 83 100 120 100 80 100-120 80-100 60 60-80 40-60 40 20-40 0-20 20 0 100 -700 -600 -500 -400 300 -300 -200 Ch. Brönnimann, SLS
Paul Scherrer Institut Pixel: Comparator and trimming AC-coupled comparator with diode feedback •simple inverter as comparator •comparator biasing done via pn-junction of the diode -> expect lower threshold variations on the chip •radiation insensitive •low power consumption global local Level shift Threshold setting Comp Dis T3 T1 T2 µ I =5 A b Outc 100f µ I ~1 A Inc c0 Vtrim µ I ~0.2 A c Ch. Brönnimann, SLS
Paul Scherrer Institut Comparator Results ! Minimum Threshold < 700e - ! Threshold variation: 130 e- untrimmed Trimbits SLS04 1200 DVthr [e] 1100 Threshold trimming: 1000 900 Trim1 800 Very low trim currents Trim2 700 Trim4 600 Trim7 500 Power 400 300 200 100 0 4.4 4.35 4.3 4.25 4.2 4.15 4.1 Vtrim [V] Ch. Brönnimann, SLS
Paul Scherrer Institut SLS03: 2cm long column biased via periphery 90 18 1 supplies 1. ∆ [V] supply in [V] out [V] VD+ 5.025 4.81 -0.22 VD- 0.000 0.22 +0.22 VA+ 5.024 4.93 -0.09 VA- 0.000 0.10 +0.10 VSF- 1.012 1.14 +0.13 VC- 2.983 3.06 +0.08 VGND 3.741 3.50 -0.24 ± 0.00 Vsh 3.741 3.74 Vg+ 5.024 4.92 -0.10 VC+ 5.024 4.95 -0.07 160 Amplitude [mV] AOUT of Pixel #18 and #90 140 120 100 80 60 40 20 Pixel 18 0 Pixel 90 time [ns] -20 -40 -200 0 200 400 600 800 1000 1200 1400 Ch. Brönnimann, SLS
Paul Scherrer Institut SLS05 Architecture Row Control Vrf Vrfs RTIN + Pixel Shift 30f 10f 1.5f Dis 200f 200f Pr Pad Sh + LS Comp 100f Vcomp Φ R 1 Trim Shift VC- comp Phi1 15-bit Φ R 2 Clockgen clk counter { 0: Readout bit 1 Phi2 RS&CS 1: Count Trim In Shift shift shift shift shift shift Xor Bit1 Bit2 Bit3 Bit4 Bit5 bit 2 XOR RS&CS PSEL & Shift shift shift shift Bit15 Bit14 Bit13 Shift Column Cal In Clk CS Dis Aout Control Shift & & > 1: CS active RTOUT 0: Selected pixel in cnt mode CHSEL CTOUT Shift DIN DCLK EN PSEL CAL VA- FF Chip Control CHSEL & CTOUT Shift Shift VD+ CHSEL Φ C Φ2 C 1 DOUT AOUT CHSEL PSEL CTIN CTOUT Ch. Brönnimann, SLS
Paul Scherrer Institut Final Chip: Yield estimation Yield measurements of SLS02 chip (22x30 pixels): Defects due to dynamic logic (Semi-static SR in Pixels): 3.8x10 -4 /bit -> 5.8x10 -3 /pixel (Yield for 85 pixel column: 60%) Defects in analog part: 3/19=0.842/chip Yield estimation for 48 x 85 pixel chip XY-Adressing, 133 SR-cells: 0.898 Analog part 0.346 30 bad pixels 0.916 Expected overall yield 0.28 Binomial Distribution 1.000E+00 8.000E-01 Sum Probability 6.000E-01 4.000E-01 2.000E-01 0.000E+00 4045 4050 4055 4060 4065 4070 4075 4080 4085 Nr of Pixels working Ch. Brönnimann, SLS
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