Placement Challenges for Structured Placement Challenges for - PowerPoint PPT Presentation

Placement Challenges for Structured Placement Challenges for Structured g g ASICs ASICs Herman Schmit Herman Schmit VP of Technology VP of Technology VP of Technology VP of Technology eASIC Corporation eASIC Corporation 1

Custom IC Design Starts Decreasing Custom IC Design Starts Decreasing Custom IC Design Starts Decreasing Custom IC Design Starts Decreasing ASIC & ASSP Design Starts (Tape Outs) ASIC & ASSP Design Starts (Tape Outs) g g ( ( p p ) ) 12,000 ASSP 10,000 ASIC sign Starts sign Starts 8,000 umber of De umber of De 6,000 4,000 Nu Nu 2,000 0 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 Source: Gartner Dataquest Estimates, November 2007 * Only 250 design starts projected in 2030! (sour (source eASI e eASIC) C)

Causes of the Decline of Design Starts Causes of the Decline of Design Starts g • • Costs: Costs: • Masks • Masks M M k k • EDA tools • EDA tools • Complexity, Intellect • Complexity, Intellect C C l l it it I t ll I t ll t t • • Verification effort is huge Verification effort is huge • Escalating costs lead to combined “super” chips, that further • Escalating costs lead to combined “super” chips, that further escalate verification costs escalate verification costs • • These do not get any better in the future… Th Th These do not get any better in the future… d d t t t t b tt b tt i i th th f t f t • Process variation, manufacturability, etc. • Process variation, manufacturability, etc. • • The contract is broken… Reasonable sized teams can’t make The contract is broken… Reasonable sized teams can’t make chips chips 3

Why a New ASIC? Why a New ASIC? y • • FPGAs cannot close the performance/power gap FPGAs cannot close the performance/power gap • • ASSPs cannot provide the customization required to differentiate products ASSPs cannot provide the customization required to differentiate products ASSPs cannot provide the customization required to differentiate products ASSPs cannot provide the customization required to differentiate products • • Do you need to specify 100s of layers to get customization you want? Do you need to specify 100s of layers to get customization you want? • • Can you get other advantages of FPGAs and ASSPs: Can you get other advantages of FPGAs and ASSPs: • • Preverified interfaces, IP, etc. Preverified interfaces, IP, etc. • • eASIC Solution: eASIC Solution: User customizes one via layer � cheap User customizes one via layer � cheap • • • • All other mask costs are amortized over all customers for that standard part All other mask costs are amortized over all customers for that standard part • • Simplified flow Simplified flow • • • • Manufacturability thru regularity Manufacturability thru regularity Manufacturability thru regularity Manufacturability thru regularity • • Reduced turn-around-time Reduced turn-around-time 4

Nextreme Family: 90nm Nextreme Family: 90nm y eCells Approx BRAM PLLs User IO storage Gates NX750 55,296 750K 864Kb 4 298 NX1500 NX1500 100 352 100,352 1 5M 1.5M 1 5Mb 1.5Mb 6 6 450 450 NX2500 169,984 2.5M 2.7Mb 8 584 NX4000 276,480 4.0M 4.3Mb 8 742 NX5000 NX5000 358 400 358,400 5 0M 5.0M 5 6Mb 5.6Mb 8 8 790 790 5

Differences from the ASIC EDA Problem Differences from the ASIC EDA Problem • • Nothing fundamentally new, just a new mix of ingredients Nothing fundamentally new, just a new mix of ingredients • • Logic Synthesis and Technology Mapping Logic Synthesis and Technology Mapping • Small size LUTs • Small size LUTs Small size LUTs Small size LUTs ASIC/FPGA like ASIC/FPGA like ASIC/FPGA like ASIC/FPGA like • • Placement and Buffering Placement and Buffering • Number and size of place able objects • Number and size of place-able objects • Number and size of place able objects • Number and size of place-able objects ASIC like ASIC like ASIC like ASIC like • Legalization due to site compatibility • Legalization due to site compatibility FPGA like FPGA like Focus • Legalization due to intrinsic resources (clocks) • Legalization due to intrinsic resources (clocks) Legalization due to intrinsic resources (clocks) Legalization due to intrinsic resources (clocks) FPGA like FPGA like FPGA like FPGA like • Buffering needs to be done, but pre-allocated • Buffering needs to be done, but pre-allocated Unique Unique • • Routing Routing Routing Routing • “Embedding” like FPGAs, but with much more flexibility • “Embedding” like FPGAs, but with much more flexibility 6

Placement Legalization: Site Compatibility Placement Legalization: Site Compatibility g g p p y y • Different cell types: logic, flip-flops, memories, buffers, • Different cell types: logic, flip-flops, memories, buffers, IO and system resources (PLLs, DLLs, etc) IO and system resources (PLLs, DLLs, etc) • Instances must go exactly on compatible site • Instances must go exactly on compatible site g g y y p p mem2 mem1 mem1 mem2 mem2 2 mem1 mem2 Logic Cells Flipflop Cells 7

Placement Legalization: Intrinsic Resources Placement Legalization: Intrinsic Resources g • • Clocks (and resets) are distributed globally with down-selection Clocks (and resets) are distributed globally with down-selection at different physical locations at different physical locations at different physical locations at different physical locations • Usually hierarchical, logically and physically • Usually hierarchical, logically and physically • • E Each region can have N clocks selected from among the Each region can have N clocks selected from among the E h h i i h h N l N l k k l l t d f t d f th th surrounding regions surrounding regions DFF DFF DFF DFF mem1 mem1 DFF DFF DFF DFF Region A Region A Region A Region A Region B 8

Our Current Solution Our Current Solution • Using adapted version of Magma ASIC tools • Using adapted version of Magma ASIC tools • Use ASIC physical synthesis thru global placement • Use ASIC physical synthesis thru global placement • Local heursitics to move objects to legal solution • Local heursitics to move objects to legal solution j j g g • “Optimal” global place to legal site degrades results • “Optimal” global place to legal site degrades results • Symptoms of the heuristics • Symptoms of the heuristics • Symptoms of the heuristics • Symptoms of the heuristics • The Smear • The Smear • The Yank • The Yank • The Tangle • The Tangle g 9

Symptom 1: The Smear Symptom 1: The Smear y p y p • • Global placement resolved overlap but not site legality Global placement resolved overlap but not site legality • • Getting from the no-overlap placement to legal placement… G Getting from the no-overlap placement to legal placement… G i i f f h h l l l l l l l l l l 3 1 4 1 2 3 4 1 2 3 4 2 5 8 5 6 7 8 6 9 7 9 A A A A 10

Symptom 2: The Yank Symptom 2: The Yank y p y p • • Clock Legalization takes advantage of unallocated sites first Clock Legalization takes advantage of unallocated sites first • • S Some elements moved significantly from their original location Some elements moved significantly from their original location S l l d i d i ifi ifi l f l f h i h i i i i i l l l l i i • Impact: Timing degradation • Impact: Timing degradation Clock Regions w/ “Slack” Cl k R i / “Sl k” Available sites for violators may not be nearby y y Clock Region Violations 11

Symptom 3: The Tangle Symptom 3: The Tangle y p y p g g • Routability Impact of Clock Legalization • Routability Impact of Clock Legalization 12

How to Solve These Problems? How to Solve These Problems? • • Option A: Improve the Architecture Option A: Improve the Architecture • Build in much more flexibility so that • Build in much more flexibility so that • Build in much more flexibility so that • Build in much more flexibility so that • StdCell Solution maps much better to the Structured Solution • StdCell Solution maps much better to the Structured Solution • More clock domains per region • More clock domains per region • Problem: Hard to do with hard blocks (memories, IOs, etc) • Problem: Hard to do with hard blocks (memories, IOs, etc) • Problem: chicken-and-egg • Problem: chicken-and-egg • Few user designs or tools when the architecture is finalized • Few user designs or tools when the architecture is finalized • Problem: simple designs pay for the complexity of hard designs • Problem: simple designs pay for the complexity of hard designs • • Option B: Improve the Software Option B: Improve the Software • • Our next generation will do both, carefully… Our next generation will do both, carefully… 13