Parts 3 and 4 Satnam Singh Microsoft Research Cambridge Overview - PowerPoint PPT Presentation

Introduction to VHDL Parts 3 and 4 Satnam Singh Microsoft Research Cambridge

Overview • Asynchronous and Synchronous resets • std_logic and resolved signals • 3 counter implementations • Test bench • Configurations • use of wat ; in test benches

Quiz 3 entity stimuli1 is end entity stimuli1 ; architecture demo of stimuli1 is signal x : bit ; begin process begin x <= '0' ; wait for 50 ns ; x <= '1' ; wait for 50 ns ; end process ; end architecture demo ;

wait ; entity stimuli2 is end entity stimuli2 ; architecture demo of stimuli2 is signal x : bit ; begin process begin x <= '0' ; wait for 50 ns ; x <= '1' ; wait ; end process ; end architecture demo ;

-- counter_package.vhd package counter_package is constant counter_bits : positive := 16 ; subtype count_type is natural range 0 to 2**counter_bits - 1 ; component counter is port (signal clk : in bit ; signal count : out count_type) ; end component counter ; end package counter_package ; use work.counter_package.all ; entity counter is port (signal clk : in bit ; signal count : out count_type) ; end entity counter ;

-- counter_behav.vhd use work.counter_package.all ; architecture behav of counter is begin counter_process : process variable counter_value : count_type := 0 ; begin wait until clk'event and clk='1' ; counter_value := (counter_value + 1) mod 2**counter_bits ; count <= counter_value ; end process counter_process ; end behav ; -- run with: force clk 0, 1 -repeat 50 ns

use work.counter_package.all ; use work.bitstoint_package.all ; architecture rtl of counter is begin counting : process variable count_vec : bit_vector (2 downto 0) := (others => '0') ; begin wait until clk'event and clk='1' ; count_vec(0) := not count_vec(0) ; if count_vec(0) = '0' then count_vec(1) := not count_vec(1) ; end if ; if count_vec(0) = '0' and count_vec(1) = '0' then count_vec(2) := not count_vec(2) ; end if ; count <= bitsToInt (count_vec) ; end process counting ; end rtl ;

use work.bitstoint_package.all ; use work.toggle_package.all ; architecture struct of counter is signal counter_bits : bit_vector (0 to counter_size-1) ; signal invclk : bit ; begin invclk <= not clk ; tgl0 : toggle port map (invclk, counter_bits(0)) ; counters : for for i in in 1 to counter_size - 1 generate generate cntr : toggle port map (counter_bits(i-1), counter_bits(i)) ; end generate end generate counters ; count <= bitsToInt (counter_bits) ; end struct ;

entity counter_tb is end entity counter_tb ; use work.counter_package.all ; architecture test1 of counter_tb is signal clk : bit ; signal behav_count, rtl_count, struct_count : count_type ; begin -- Instances of the two circuits to be compared. behav_counter : entity work.counter (behav) port map (clk, behav_count) ; rtl_counter : entity work.counter (rtl) port map (clk, rtl_count) ; struct_counter : entity work.counter (struct) port map (clk, struct_count) ;

Configurations use work.counter_package. all ; configuration counter_behav_tb of counter_tb is for test1 for counter_inst : counter use entity work.counter (behav) ; end for ; end for ; end configuration counter_behav_tb ;

Quiz 4 package resetable_toggle_package is component resetable_toggle is port (signal clk, rst : in bit ; signal t : out bit) ; end component resetable_toggle ; end resetable_toggle_package ; entity resetable_toggle is port (signal clk, rst : in bit ; signal t : out bit) ; end entity resetable_toggle ;

Resolution Functions package resolved_bit_package is function resolve_b e_bit its (contribution : in bit_vector) return bit ; subtype resolved_bit is resolve_bits bit ; end package resolved_bit_package ; package resolved_bit_package is function resolve_b e_bit it (contribution : in bit_vector) return bit is variable result : bit := '1' ; begin for i in contribution'range loop result := result and contribution(i) ; end loop ; return result ; end function resolve_bit ; end package resolved_bit_package ;

Multiple Drivers entity multiple_bit is end entity multiple_bit ; use work.resolved_bit_package.all ; architecture demo of multiple_bit is signal a : resolved_bit ; signal x, y : bit ; begin a <= x ; a <= y ; end architecture demo ;

std_ulogic • type std_ulogic = (‘U’, -- unitialised ‘X’ , -- forcing unknown ‘0’, -- forcing zero ‘1’, -- forcing one ‘Z’, -- high impedance ‘W’, -- weak unknown ‘L’, -- weak zero ‘H’, -- weak one ‘ - ’) -- don’t know

std_logic subtype subtype std_logic is is resolved std_ulogic ; type type std_logic_vector is ar array (natural range range <>) of of std_logic ;