Overview State Machines Introduction to Structured VLSI Design - PowerPoint PPT Presentation

Overview • State Machines Introduction to Structured VLSI Design • Moore ‐ FSM’s • Mealy • Exercise Joachim Rodrigues Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Mealy vs. Moore Mealy vs. Moore • Moore • Mealy – Out = F(Current state) – Out = F(Inputs, Current state) – Next state = F(Inputs, current state) – Next state = F(Inputs, Current state) 10 S2 10/0 10/0 S2 Y=0 11 11/1 S3 A1 A1 S1 S3 11/1 Y=1 Y S1 Y Y=0 A2 A2 00/0 A1 A2 = 00 S4 S4 01/1 01 Y=1 A1 A2 / Y 01/1 Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

Mealy vs. Moore Mealy • In some situations a Mealy machine can be specified R and implemented using less states because it is FSM1 FSM2 capable of producing different outputs in a given A state. 1/1 0/0 • In some situations a system using a Mealy machine S0 S1 can be faster because an output may be produced 1/1 immediately instead of at the next clock tick. • A Moore machine produces glitch free outputs. 0/0 • The outputs from a Moore machine are available to • When in s0, a Mealy machine may produce A ‐ >1 its environment for almost a clock cycle, and in some immediately in response to R ‐ >1 situations this may allow using a faster cock. Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Moore A small exercise /problem R • Pushing: * { A; B; B; A } => Open FSM1 FSM2 A A 0 Lock Open 1 1 B FSM 0 S0 S1 1 A=0 A=1 Clk 0 • Draw a state graph for the Lock ‐ FSM • … a Moore machine is not able to produce A ‐ >1 until the next clock when it enters s1 Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s

State Graph for lock ‐ FSM FSM Exercise (”Homework”) Marge wants to install an alarm that triggers as soon as Assuming that A and B are never pressed at the same time … somebody enters the kitchen. The alarm should have several alert levels. A etc… • level0: Neither Homer nor Bart is in the kitchen sA sABB sAB sABBA • level1: Bart but not Homer is in the kitchen L=0 L=0 L=0 L=1 • level2: Homer but not Bart is in the kitchen A A B B • level3: Homer and Bart are in the kitchen A B B A A s0 s1 s2 s3 L=0 L=0 L=0 L=0 B A To detect who enters or leaves the kitchen 2 sensors g1 and g0 are installed in the door frame as depicted. The sensors emit a ‘1’ as soon as their reflection is sABBB B interrupted. If Bart enters the kitchen only g0 will emit a ‘1’. Homer is always L=0 leaning forward when he is entering the kitchen, and, thus, g1 will always be interrupted before g0. Once they have decided to go into the kitchen they will go through the door. However, if they are in the kitchen they always can leave, e.g., Hmmm: Is this a Mealy FSM or a Moore FSM? level3 changes to level2. The size of Homers hips and belly prevent them from entering the kitchen simultaneously. The clock frequency is 1MHz. Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se FSM’s