Paper Review DIVA - A reliable substrate for Deep Submicron Microarchitecture Design - Todd Austin, Univ. of Michigan (1999) ECE1718 MCA - K.P. Tang November 2008 Overview • Background – Deep submicron challenges – Verification, testing, validation • Motivation – simply processor verification and lower test cost • Diva Architecture – Chkcomp, Chkcomm, Watchdog Timer • How it works • Diva observations • Summary 2 1
Deep submicron challenges • Smaller geometry – performance, power, cost • Increasing complexity – design, test, manufacturing • Time to market, get it right the first time • Costs – NRE, design, test, manufacturing – opportunity cost (market share) • Values – Correctness, performance, cost, time 3 Verification, testing, validation • Verification – Functionality and performance – Simulation and formal verification • Testing – Manufacturing • Validation – System integration – Did we build the right system? • Verification needs to cover all programs, corner cases – Verification gap 4 2
Verification gap 5 Sources of errors • Functional – Logic (>60%) • Timing – Glitches, races, speed • Manufacturing – Defects • Others – Process, operating condition (temperature/voltage) variations – EM interference, radiation 6 3
Design re-spins Many designs have one or more re-spins Delays in re-spins = Lost time to market 7 DIVA checker • DIVA – Dynamic Implementation Verification Architecture • Increase processor design reliability • Separate microarchitectural processor design and verification • Detect and fix incorrect operation • Become a run-time checker • Lower verification costs and risks • Improve time-to-market 8 4
DIVA core and checker IF – Intr. Fetch ID – Intr. Decode REN – Rename REG – Register EX – Execution MEM – Memory CT – Commit CHK – Check WT – Watchdog Timer 9 Source: DIVA Source: DIVA - - Todd Austin, Univ. of Michigan Todd Austin, Univ. of Michigan DIVA checker • CHKcomp verifies results • CHKcomm verifies register/memory inputs • Watchdog timer detects lockups • Simple, in-order scheduler, no reorder, low latency, accurate 10 Source: DIVA - Todd Austin, Univ. of Michigan 5
DIVA checker architecture 11 Source: DIVA - Todd Austin, Univ. of Michigan DIVA check mode 12 Source: DIVA - Todd Austin, Univ. of Michigan 6
DIVA recovery mode 13 Source: DIVA - Todd Austin, Univ. of Michigan DIVA observations Complex core processor Checker processor • Focus on fast, speculative, and • Simple and low cost processor complex core design core • Branch predictions • Take advantages of main core branch predictions and cache • Cache prefetches prefetches • Focus on fault detection and correction (design errors, electrical faults, silicon defects, and even core failures) • Checker must be high accuracy 14 and reliable Source: DIVA - Todd Austin, Univ. of Michigan 7
Beta release and launch Previous launch Previous beta time 15 Source: DIVA - Todd Austin, Univ. of Michigan Self-tuned systems • Self tuning to maximize operating performance – Built-in design margins from designers – Speed binning at manufacturing – Optimize operating frequency with voltage and temperature inputs 16 Source: DIVA - Todd Austin, Univ. of Michigan 8
DIVA checker verification • Simple checker processor core requires complete functional verification 17 Source: DIVA - Todd Austin, Univ. of Michigan DIVA checker core BIST Manufacturing defects 18 Source: DIVA - Todd Austin, Univ. of Michigan 9
If checker processor fail to check? Transient faults 19 Source: DIVA - Todd Austin, Univ. of Michigan Replicate checker core Core redundancy 20 Source: DIVA - Todd Austin, Univ. of Michigan 10
Summary • Introduced DIVA core and DIVA checker • DIVA can separate processor core design from traditional costly and lengthy core verification • DIVA pipelined checker core can be simple, fast (latency insensitive), and low cost • Core processor can tolerate permanent and transient errors • Beta release can help overlap processor launch with verification • Clock and voltage tuning system can optimize circuit operations • DIVA must be reliable and functionally correct. 21 Source: DIVA - Todd Austin, Univ. of Michigan Backup slides 22 Source: DIVA - Todd Austin, Univ. of Michigan 11
Example operations 23 Source: DIVA - Todd Austin, Univ. of Michigan Register file and cache bandwidth 1 extra memory port is good enough 24 R-4 extra register file ports, M-1 extra memory port Source: DIVA - Todd Austin, Univ. of Michigan 12
Checker latency Minimal effect on core performance 25 Source: DIVA - Todd Austin, Univ. of Michigan Exception rates Worst case performance 26 Source: DIVA - Todd Austin, Univ. of Michigan One exception per x instruction 13
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