9/23/2014 Overview • Problem and motivation ECE 553: TESTING AND • Fault simulation algorithms TESTABLE DESIGN OF • Serial • Parallel DIGITAL SYSTES DIGITAL SYSTES • Deductive • Concurrent • Other algorithms • Random Fault Sampling • Summary Fault Simulation 9/23/2014 2 Usages of Fault Simulators Problem and Motivation • Fault simulation Problem: Given • Test grading – as explained before A circuit • Test Generation A sequence of test vectors A fault model • Fault diagnosis – Determine Fault coverage - fraction (or percentage) of modeled faults • Design for test (DFT) – identification of D i f (DFT) id ifi i f detected by test vectors points that may help improve test quality Set of undetected faults • Motivation • Fault-tolerance – identification of damage a Determine test quality and in turn product quality fault can cause Find undetected fault targets to improve tests 9/23/2014 3 9/23/2014 4 Fault Simulator in a VLSI Design Alternatives and Their Limitations Process • Prototyping with fault injection capabilities Verification Verified design – Costly input stimuli netlist – Limited fault injection capability – Design changes hard to implement Fault simulator Test vectors – Long lead time Modeled Remove Test Delete • Hardware emulators fault list tested faults compactor vectors – Costly Fault Low Test – Require special hardware coverage generator Add vectors ? Adequate Stop 9/23/2014 5 9/23/2014 6 1
9/23/2014 Fault Simulation Scenario Fault Simulation Scenario (continued) • Circuit model: mixed-level • Faults: • Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals • Mostly single stuck-at faults • High-level models (memory, etc.) with pin faults • Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use • Signal states: logic g g • Equivalence fault collapsing of single stuck-at faults • Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits • Fault-dropping -- a fault once detected is dropped from • Four states (0, 1, X, Z) for sequential MOS circuits consideration as more vectors are simulated; fault- dropping may be suppressed for diagnosis • Timing: • Fault sampling -- a random sample of faults is simulated • Zero-delay for combinational and synchronous circuits when the circuit is large • Mostly unit-delay for circuits with feedback 9/23/2014 7 9/23/2014 8 Fault Simulation Algorithms Serial Algorithm • Algorithm: Simulate fault-free circuit and save • Serial responses. Repeat following steps for each fault in the fault list: • Parallel • Modify netlist by injecting one fault • Deductive • Simulate modified netlist, vector by vector, comparing responses • Concurrent • Concurrent with saved responses • Others • If response differs, report fault detection and suspend simulation of remaining vectors – Differential • Advantages: – Parallel pattern • Easy to implement; needs only a true-value simulator, less memory – etc. • Most faults, including analog faults, can be simulated 9/23/2014 9 9/23/2014 10 Fault Injection Serial Algorithm (Cont.) • Disadvantage: Much repeated computation; CPU time • Modifying netlist for every run can be prohibitive for VLSI circuits expensive • Alternative: Simulate many faults together • Alternative – Check if a net is faulty or fault-free Test vectors Fault-free circuit Comparator f1 detected? • If faulty change its value to the stuck-value If f l h i l h k l Circuit w ith fault f1 Else leave it to the computed value Comparator f2 detected? – Mux based fault insertion Circuit w ith fault f2 • Use additional variables and compute the value based on the signal value and the value in the additional variable Comparator fn detected? Circuit w ith fault fn 9/23/2014 11 9/23/2014 12 2
9/23/2014 Parallel Fault Sim. Example Parallel Fault Simulation Bit 0: fault-free circuit • Compiled-code method; best with two-states (0,1) Bit 1: circuit w ith c s-a-0 • Exploits inherent bit-parallelism of logic Bit 2: circuit w ith f s-a-1 operations on computer words 1 1 1 c s-a-0 detected • Storage: one word per line for two-state simulation a 1 0 1 1 1 1 1 0 1 • Multi-pass simulation: Each pass simulates w -1 e b 1 0 1 c new faults, where w is the machine word length s-a-0 g 0 0 0 • Speed up over serial method ~ w -1 • Not suitable for circuits with timing-critical and d f s-a-1 0 0 1 non-Boolean logic 9/23/2014 13 9/23/2014 14 Deductive Fault Sim. Deductive Fault Simulation Example • One-pass simulation Notation: L k is fault list for line k • Each line k contains a list L k of faults detectable k n is s-a-n fault on line k on k • Following true-value simulation of each vector, L e = L a U L c U { e 0 } { a 0 } 1 = { a 0 , b 0 , c 0 , e 0 } fault lists of all gate output lines are updated using g p p g a set-theoretic rules, signal values, and gate input { b 0 , c 0 } 1 e 1 b c 1 fault lists { b 0 } g • PO fault lists provide detection data f 0 d U L g = ( L e L f ) U { g 0 } • Limitations: { b 0 , d 0 } = { a 0 , c 0 , e 0 , g 0 } { b 0 , d 0 , f 1 } • Set-theoretic rules difficult to derive for non-Boolean gates Faults detected by • Gate delays are difficult to use the input vector 9/23/2014 15 9/23/2014 16 Concurrent Fault Simulation Conc. Fault Sim. Example • Event-driven simulation of fault-free circuit and only b 0 c 0 e 0 a 0 those parts of the faulty circuit that differ in signal states 0 1 1 1 from the fault-free circuit. 0 0 0 0 0 1 0 1 • A list per gate containing copies of the gate from all 1 a 1 1 faulty circuits in which this gate differs. List element 1 1 e b 1 contains fault ID, gate input and output values and contains fault ID gate input and output values and 1 1 1 c c 1 g internal states, if any. 0 0 1 0 a 0 c 0 e 0 b 0 • All events of fault-free and all faulty circuits are d f 0 0 0 0 1 0 implicitly simulated. 0 0 1 0 0 0 • Faults can be simulated in any modeling style or detail 1 1 1 supported in true-value simulation (offers most 0 1 1 b 0 d 0 f 1 0 1 g 1 d 0 f 1 flexibility.) 0 1 1 1 0 1 0 • Faster than other methods, but uses most memory. 9/23/2014 17 9/23/2014 18 3
9/23/2014 Other Fault Simulation Algorithms Fault Sampling • A randomly selected subset (sample) of faults is • Parallel pattern single fault simulation simulated. (PPSFP) • Measured coverage in the sample is used to – Simulate many vectors in parallel Simulate many vectors in parallel estimate fault coverage in the entire circuit. estimate fault coverage in the entire circuit – Inject only one fault – hence one event • Advantage: Saving in computing resources (CPU time and memory.) – Simulate the circuit from the fault site • Disadvantage: Limited data on undetected faults. – Limitation – well suited for combinational circuits only 9/23/2014 19 9/23/2014 20 Motivation for Sampling Random Sampling Model Detected Undetected fault fault • Complexity of fault simulation depends on: All faults w ith • Number of gates Random a fixed but • Number of faults unknow n picking coverage coverage • Number of vectors • Number of vectors • Complexity of fault simulation with fault sampling N s = sample size N p = total number of faults N s << N p depends on: (population size) c = sample coverage • Number of gates C = fault coverage (unknow n) (a random variable) • Number of vectors 9/23/2014 21 9/23/2014 22 Probability Density of Sample Sampling Error Bounds Coverage, c C (1 - C ) | x - C | = 3 [ -------------- ] 1/2 ( x--C ) 2 N s -- ------------ 2 σ 2 1 Solving the quadratic equation for C , w e get the p ( x ) = Prob( x < c < x + dx ) = -------------- e 3-sigma (99.7% confidence) estimate: σ ( 2 π) π) 1/2 σ 4.5 C (1 - C ) ------- [1 + 0.44 N s x (1 - x )] 1/2 ± , σ 2 = ------------ C 3 σ = x Variance , σ N s N s p ( x ) Sampling σ σ Where N s is sample size and x is the measured fault error Mean = C coverage in the sample. Example: A circuit w ith 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in x 1.0 a random sample of 1,000 faults is 88.7%. The above C -3 σ x C +3 σ C ± formula gives an estimate of 88.7% 3%. CPU time for Sample coverage sample simulation w as about 10% of that for all faults. 9/23/2014 23 9/23/2014 24 4
9/23/2014 Summary • Fault simulator is an essential tool for test development. • Concurrent fault simulation algorithm offers the best choice. • For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives) synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5.5.6.) • For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. 9/23/2014 25 5
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