Overview Motivation ECE 553: TESTING AND Logic Modeling - PDF document

9/5/2014 Overview • Motivation ECE 553: TESTING AND • Logic Modeling TESTABLE DESIGN OF – Model types – Models at different levels of abstractions – Models at different levels of abstractions DIGITAL SYSTES DIGITAL SYSTES – Models and definitions • Summary Logic Modeling 9/5/2014 2 Motivation Logic Modeling – Model types – Models are often easier to work with • External • Behavior representation – Models are portable – System at I/O level • Internal – Timing inf provided – Models can be used for simulation, thus representation – Internal details missing avoiding expensive hardware/actual circuit avoiding expensive hardware/actual circuit • Functional implementation – DC behavior – no timing – Nearly all engineering systems are studied • Structural using models – Gate level description – All the above apply for logic as well as for fault • Models are often described using an hierarchy modeling 9/5/2014 3 9/5/2014 4 Modeling Levels Hierarchical Model: A Full-Adder Modeling Signal Application Circuit Timing level description values Architectural HA; Programming Clock Function, 0, 1 and functional c inputs: a, b; language-like HDL boundary behavior, RTL verification a outputs: c, f; e Connectivity of Zero-delay Logic AND: A1, (a, b), (c); Logic 0, 1, X unit-delay, verification Boolean gates, d AND: A2, (d, e), (f); and Z f multiple- flip-flops and p p and test OR: O1 (a b) (d); OR: O1, (a, b), (d); b b transistors delay HA NOT: N1, (c), (e); Transistor size Logic Sw itch 0, 1 Zero-delay and connectivity, and X verification node capacitances FA; D A Carry inputs: A, B, C; Transistor technology Analog Timing Fine-grain Timing HA1 E F outputs: Carry, Sum; data, connectivity, voltage B timing verification HA2 Sum HA: HA1, (A, B), (D, E); node capacitances C HA: HA2, (E, C), (F, Sum); Digital timing Continuous Circuit Tech. Data, active/ Analog and analog OR: O2, (D, F), (Carry); time voltage, passive component circuit connectivity current verification 9/5/2014 5 9/5/2014 6 1

9/5/2014 Logic Models and definitions* Logic Models and definitions (2) • Combinational circuit models • Program model of a circuit – Function expressed as truth-table or cubes – Express circuit (gate level) as a program consisting of interconnected logic operations – Cubes and cube intersection can be used during simulation – Execute the program to determine circuit output for varying • Sequential Circuits inputs inputs – Structure represented as a collection of flip-flops feeding • RTL model combinational logic – Higher level model of the circuit – Time frame expansion is possible • HDL model • Binary Decision Diagrams (BDD) – Examples at this level are verilog HDL and VHDL * Ref: Abramovici et. al, Digital system testing and testable design 9/5/2014 7 9/5/2014 8 Logic Models and definitions (3) Netlist Format: Two Examples • Structural model ISCAS format UW format – External representation in the form of netlist – Examples of this are uw format, iscas format, EDIF, … # gate connected to output = gate(inputs) – Some keywords used in such representation INPUT(G1) 1 PI 4, 5 ; • Primary inputs and Primary outputs 2 PI 3, 6 ; 2 PI 3 6 INPUT(G2) INPUT(G2) • Gates: AND, OR, NOT, … 3 not 5 ; OUTPUT(G7) • Storage: latch, flip-flop • Connections: lines, nets 4 not 6 ; G3 = NOT(G2) • Fanin: number of inputs to a gate G4 = NOT(G1) 5 and 7 ; • Fanout: number of lines a signal feeds G5 = AND(G1, G3) 6 and 7 ; • Fanoutfree circuit: every line or gate has a fanout of one G6 = AND(G2, G4) 7 or 8 ; G7 = OR(G5, G6) 8 PO ; 9/5/2014 9 9/5/2014 10 Logic Models and definitions (4) Logic Models and definitions (5) • Structural model • Additional useful terms – Internal representation in the form of tables – Graph representation • Tables of gates and storage elements (names) – Reconvergent fanouts • Tables of connections – Stems and branches Stems and branches • Tables of fanin and fanouts – Logic levels in a circuit – Objective is to make the storage and search processes – “levelization” of a circuit (integral part of simulation) more efficient – Knowledge of data structures and algorithms is very useful 9/5/2014 11 9/5/2014 12 2

9/5/2014 Summary • Modeling of logic circuit offers many advantages • Many modeling levels exist and are used • Gate level models are most prevalent in logic testing 9/5/2014 13 3