Outline Introduction Delay Test Issues Our Solutions Improved - PDF document

DESIGN FOR AT-SPEED DELAY TEST Youhua Shi Information Technology Research Organization Waseda University Outline • Introduction • Delay Test Issues • Our Solutions – Improved Launch Delay Testing – Power-aware Test Technique • Conclusions

Introduction What is Driving Modern Test Technology? • SoC Design – Massive Integration – Time-to-Market • Deep-Submicron/Nanometer Design – New Failure Modes – Massive Integration DSM/Nanometer Design • In DSM design problem focus moved – (.5u) Delay moved into route – (.35) Clock skew and routing congestion – (.25) Power delivery • In Nanometer design – (180) Faults Stuck-at Functional predominantly in route Test Test Complete – (130) Background Test Strategy leakage in tens of mA Delay Test IDDQ Test – (<90) ???

Why Do At-Speed Delay Testing? • Timing-Related Defects – a 20X increase in timing-related defects moving from 180nm to 130nm – 20 – 50% of the test escapes are timing related • To detect the timing related Source: NVIDIA 2003 defect 2 conditions are required: – The pattern should generate a transition – The transition propagation should be captured at-speed Complex Failure Modes Require New Design for Test techniques. At-Speed Delay Test Functional Stuck-at • At-speed delay testing is a MUST!! Test Test Complete Test – improve manufacturing quality Strategy – maintain DPM rates in nanometer designs Delay Test IDDQ Test Fault site • Delay fault models – Transition fault model For testing gross delay defects at a node • Tests combined delay through all gates of a path • Requires paths as input – Path delay fault model Faulty path For testing distributed delays along a path • Tests for a gross delay potential at each gate terminal • Paths are automatically selected to test transition faults

Transition Delay Test Launch-on-shift Launch-on-capture Capture Launch Capture Launch CK CK SE SE Shift Shift Last Shift Shift Shift Shift Dead Shift Cycles LOS vs. LOC Launch-on-shift Launch-on-capture • Advantages • Advantages – Combinational ATPG – Fewer requirements on the scan control logic and is • Higher coverage, fewer easier pattern, faster runtime • Shifting can be done at any • Disadvantages speed – Must disable scan enable • Scan enable doesn’t have to quickly be routed as a critical clock • Scan enable must be routed or pipelined as a timing critical clock • Disadvantages – Can create non-functional – Sequential ATPG (at least 2 patterns system clock cycles) • Possible to cause overtest • Medium coverage, more Most customers use LOC delay test! patterns and longer runtime

At-speed Delay Test Issues Power, IR-drop, Small delay, frequency, etc overtest, etc Power Cost Quality Test pattern, test time, ATE, etc Fault coverage etc. Delay Test Strategy Issue I. Cost vs. Quality • Transition pattern data volume 4x-6x more than stuck-at • Method to reduce test cost – Test Compression quality • What can be done in the design? cost – Design for delay test

Solution: Improved Launch Delay Testing • Objective Capture Launch – Higher fault coverage – Less patterns CK SE • Basic Idea Shift Shift Last Shift Shift – Two launch mode • LOS mode Launch Capture – Launch-on-shift using slow scan enable CK • Mixed launch mode SE – LOC + LOS Shift Shift Shift Dead Cycles Solution: Improved Launch Delay Testing mode sel lse se d q(so) si clk

Experimental Results Concluding Remarks • DFT technique for better test quality and lower cost • Left work – ATPG development – Optimized SFF selection • Use Launch-on-Shift for majority of coverage • Use Launch-on-Capture for higher speed clock domains and critical path

Issue II. Power in Delay test • Power has become the main challenge for nanometer designs • Power consumption during test mode is higher – 3-8X as compared to functional mode – 30X in low power devices!!! • Such high difference in power consumption can lead to permanent damage • Reliability failures due to higher junction temperature and increased peak power • May result over kill by power consumption in test mode Methodology needed to be address this issue Issue II. Power in Delay test

Solution: Test Power Reduction • Test Power – Scan shift power – Capture power • Our solutions – Intelligent X-filling in test data compression (done) • Power reduction is around 40% – DFT for shift power reduction (done) • Prevent switching in the comb. logic during shift • Shift power is reduced up to 10X • However, Peak power is increased – DFT for power reduction in delay test (ongoing) Solution: Test Power Reduction • DFT for power reduction in delay test – Capture power aware ATPG – Intelligent X-filling – Transition Loading Scheme

Conclusions • Nanometer designs require delay test to maintain high test quality • Delay test increases test cost • DFT techniques could reduce test cost while maintaining high test quality • Future work – Small delay test – Avoid over kill in delay test – DFT techniques for emerging processor architecture, power-gating circuits, etc Thank You!!! • Questions ? • Comments / feedback welcome: <shi@yanagi.comm.waseda.ac.jp>