Opamp Design Project Help Session Boise, 19/Apr/2014 Vishal Saxena - PowerPoint PPT Presentation

Opamp Design Project Help Session Boise, 19/Apr/2014 Vishal Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Design Specifications Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp Vishal Saxena <vishalsaxena@boisestate.edu>

Design Equations Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Zero-Nulling R Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Voltage Buffer Compensation Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Common Gate Compensation Vishal Saxena <vishalsaxena@boisestate.edu>

Class-A Stage: Slewing Vishal Saxena <vishalsaxena@boisestate.edu>

Class-AB Stage: Floating Current Mirror Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Telescopic with Class- AB Stage Vishal Saxena <vishalsaxena@boisestate.edu>

Folded Cascode OTA Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Folded-Cascode with Class-AB Stage Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Folded-Cascode + Class-AB Stage, Full-rail input CMR Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Gain Enhancement Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – AC Response Caveat: • Don’t use this method. • Use STB analysis with iprobe instead. Vishal Saxena <vishalsaxena@boisestate.edu>

Two-Stage Opamp – Step Response Vishal Saxena <vishalsaxena@boisestate.edu>

Spectre STB Analysis • The STB analysis linearizes the circuit about the DC operating point and computes the loop-gain, gain and phase margins (if the sweep variable is frequency), for a feedback loop or a gain device [1]. • Refer to the Spectre Simulation Refrence [1] and [2] for details. Vishal Saxena <vishalsaxena@boisestate.edu>

Example Single-ended Opamp Schematic Vishal Saxena <vishalsaxena@boisestate.edu>

STB Analysis Test Bench • Pay attention to the iprobe component (from analogLib) • Acts as a short for DC, but breaks the loop in stb analysis • Place the probe at a point where it completely breaks (all) the loop(s). Vishal Saxena <vishalsaxena@boisestate.edu>

DC Annotation • Annotating the node voltages and DC operating points of the devices helps debug the design • Check device gds to see if its in triode or saturation regions Vishal Saxena <vishalsaxena@boisestate.edu>

Simulation Setup • Always have dc analysis on for debugging purpose Vishal Saxena <vishalsaxena@boisestate.edu>

Bode Plot Setup • Results->Direct Plot-> Main Form Vishal Saxena <vishalsaxena@boisestate.edu>

Open Loop Response Bode Plots • Here, f un =152.5 MHz, PM=41.8º • Try to use the stb analysis while the circuit is in the desired feedback configuration • Break the loop with realistic DC operation points Vishal Saxena <vishalsaxena@boisestate.edu>

Transient Step Response Test Bench • Transient step-response verifies the closed-loop stability • Use small as wells as large steps for characterization • iprobe acts as a short (can remove it) Vishal Saxena <vishalsaxena@boisestate.edu>

Small Step Response • Observe the ringing (PM was 41º) • Compensate more Vishal Saxena <vishalsaxena@boisestate.edu>

Large Step Response • Note the slewing in the output Vishal Saxena <vishalsaxena@boisestate.edu>

Miller Compensation • Compensation capacitor (C c ) between the output of the gain stages causes pole-splitting and achieves dominant pole compensation. VDD VDD VDD • An RHP zero exists at M7 M3 M4 1 • Due to feed-forward component of 220/2 750 Ω the compensation current (i C ). v p v m i C fb v out M1 M2 • The second pole is located at C L C C 10pF 2 i C ff 30pF • The unity-gain frequency is V bias 3 M6TL 100/2 M6TR M8T • V bias 4 A benign undershoot in step- M6BL 100/2 response due to the RHP zero M6BR M8B Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. x10  All the op-amps presented have been designed in AMI C5N 0.5 μ m CMOS process with scale=0.3 μ m and L min =2. The op-amps drive a 30pF off-chip load offered by the test-setup. Vishal Saxena <vishalsaxena@boisestate.edu>

Drawbacks of Direct (Miller) Compensation • The RHP zero decreases phase VDD VDD margin VDD M7 M3 M4 • Requires large C C for 1 220/2 compensation (10pF here for a 30pF load!). C C v m v p v out M1 M2 C L • Slow-speed for a given load, C L. 2 10pF 30pF V bias 3 • Poor PSRR M6TL 100/2 M6TR M8T V bias 4 M6BL 100/2 • Supply noise feeds to the M6BR M8B output through C C . Unlabeled NMOS are 10/2. • Large layout size. Unlabeled PMOS are 22/2. x10 Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Indirect (or Ahuja) Compensation • The RHP zero can be eliminated by VDD VDD VDD VDD blocking the feed-forward M3 M4 M9 compensation current component 1 M7 220/2 by using v m i c C c M1 M2 • A common gate stage, v out 2 M CG C L A v p • A voltage buffer, 30pF V bias3 M6TL 100/2 M6TR M10T M8T • Common gate “embedded” in the V bias4 M6BL 100/2 M6BR M8B cascode diff-amp, or M10B Unlabeled NMOS are 10/2. • A current mirror buffer. Unlabeled PMOS are 22/2. x10 • Now, the compensation current is An indirect-compensated op-amp fed-back from the output to node-1 using a common-gate stage. indirectly through a low-Z node-A. • Since node-1 is not loaded by C C , this results in higher unity-gain frequency (f un ). Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Indirect Compensation in a Cascoded Op- amp VDD VDD VDD M4T VDD VDD M3T V bias1 A i c VDD M4 VDD M4B V bias2 M3 M4 M3B M7 M7 110/2 1 220/2 1 C C v m v p M1T M2T C C v out M1 M2 v out A C L C L 2 v m v p 2 1.5pF 1.5pF 30pF M1B 10/10 M2B i c V bias3 50/2 30pF M6TL M6TR M8T V bias4 V bias3 30/2 M6BL 50/2 100/2 M6BR M8B M8T M5T V bias4 30/2 100/2 M8B Unlabeled NMOS are 10/2. M5B Unlabeled PMOS are 44/2. Unlabeled NMOS are 10/2. Unlabeled PMOS are 22/2. Indirect-compensation using Indirect-compensation using cascoded current mirror load. cascoded diff-pair.  Employing the common gate device “embedded” in the cascode structure for indirect compensation avoids a separate buffer stage.  Lower power consumption.  Also voltage buffer reduces the swing which is avoided here. Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Analytical Modeling of Indirect Compensation C c i c R c A v out v in The compensation A 2 A 1 1 2 current (i C ) is indirectly fed-back to node-1. Differential Gain Stage Amplifier Block Diagram vout  ic  1 sCc Rc 1 2 + + C c R C is the resistance g m1 v s g m2 v 1 C 2 R 1 C 1 R 2 v out attached to node-A. R c - - Small signal analytical model Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Analytical Results for Indirect Compensation j    un  p 3 p 2 p 1 z 1 Pole-zero plot LHP zero  Pole p 2 is much farther away from f un .  Can use smaller g m2 =>less power!  LHP zero improves phase margin.  Much faster op-amp with lower power and smaller C C .  Better slew rate as C C is smaller. Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Indirect Compensation Using Split-Length Devices • As VDD scales down, cascoding is becoming tough. Then how to realize indirect compensation as we have no low-Z node available? • Solution: Employ split-length devices to create a low-Z node. • Creates a pseudo-cascode stack but its really a single device. • In the NMOS case, the lower device is always in triode hence node-A is a low-Z node. Similarly for the PMOS, node-A is low-Z. Low-Z node VDD Low-Z node M1T Triode S M1T VDD W/L 1 M1 Equivalent A W/L 1 G M1 W/(L 1 +L 2 ) A Triode Equivalent W/(L 1 +L 2 ) A W/L 2 D M1B Low-Z W/L 2 node M1B Split-length 44/4(=22/2) NMOS PMOS PMOS layout Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

Split-Length Current Mirror Load (SLCL) Op-amp VDD VDD VDD M4T M3T i c A 220/2 p 2,3 M7T M3B M4B 220/2 1 M7B z 1 C C v m v p f un v out M1 M2 C L 2 2pF 30pF V bias 3 M6TL 50/2 Frequency Response M6TR M8T V bias 4 M6BL 50/2 M6BR M8B Unlabeled NMOS are 10/2. t s Unlabeled PMOS are 22/2.  The current mirror load devices are split-length to create low-Z node-A.  Here, f un =20MHz, PM=75 ° and t s =60ns. Small step-input settling in follower configuration Saxena Vishal Saxena <vishalsaxena@boisestate.edu>

SLCL Op-amp Analysis 1 1 1 g mp g mp g mp g m 1  v + A A g s gm vs mp - 1 C c C c 2 v out v out 1 1 i d2 i d1 i d1 2 2 vs vs C L vs C L  2 2 2 v=0 (a) (b) C c r op A 2 1 + + + gm vs 1 1 v 1 v sgA 1 v out g mp g mp 2 C A g m2 v 1 C 2 R 2 g mp v sgA R 1 C 1 - g - -  m 1 v g s mp  Here f z1 =3.77f un 1 2 + +  LHP zero appears at a higher C c v 1 v out frequency than f un . gm vs 1 1 C 2 R 2 i c g m2 v 1 R 1 C 1 gmp - - vout  ic 1 1  sCc gmp Saxena Vishal Saxena <vishalsaxena@boisestate.edu>