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Multi Cycle CPU Jason Mars Monday, February 4, 13 Why a Multiple - PowerPoint PPT Presentation

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Multi Cycle CPU Jason Mars Monday, February 4, 13 Why a Multiple Cycle CPU? Monday, February 4, 13 Why a Multiple Cycle CPU? The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine

  1. Multi Cycle CPU Jason Mars Monday, February 4, 13

  2. Why a Multiple Cycle CPU? Monday, February 4, 13

  3. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine Monday, February 4, 13

  4. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks Monday, February 4, 13

  5. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) Monday, February 4, 13

  6. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) Monday, February 4, 13

  7. Why a Multiple Cycle CPU? • The problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine • The solution => break up execution into smaller tasks, each task taking a cycle, di ff erent instructions requiring di ff erent numbers of cycles or tasks • Other advantages => reuse of functional units (e.g., alu, memory) • ET = IC * CPI * CT Monday, February 4, 13

  8. High Level View Monday, February 4, 13

  9. Breaking Execution into Clock Cycles • We will have five execution steps (not all instructions use all five) • fetch • decode & register fetch • execute • memory access • write-back • We will use Register-Transfer-Language (RTL) to describe these steps Monday, February 4, 13

  10. Breaking Execution into Clock Cycles Monday, February 4, 13

  11. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. Monday, February 4, 13

  12. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. • Significantly complicates control. Why? Monday, February 4, 13

  13. Breaking Execution into Clock Cycles • Introduces extra registers when: • Signal is computed in one clock cycle and used in another, AND • The inputs to the functional block that outputs this signal can change before the signal is written into a state element. • Significantly complicates control. Why? • The goal is to balance the amount of work done each cycle. Monday, February 4, 13

  14. Multi-Cycle Datapath Monday, February 4, 13

  15. Multi-Cycle Datapath • More Latches Monday, February 4, 13

  16. Multi-Cycle Datapath • More Latches • One ALU Monday, February 4, 13

  17. Multi-Cycle Datapath • More Latches • One ALU • One Memory Unit Monday, February 4, 13

  18. 1. Fetch IR = Mem[PC] PC = PC + 4 ( may not be final value of PC ) Monday, February 4, 13

  19. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  20. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) Monday, February 4, 13

  21. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) Monday, February 4, 13

  22. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) • everything up to this point must be Instruction- independent, because we still haven’t decoded the instruction . Monday, February 4, 13

  23. 2. Instruction Decode and Register Fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) • compute target before we know if it will be used (may not be branch, branch may not be taken ) • ALUOut is a new state element (temp register ) • everything up to this point must be Instruction- independent, because we still haven’t decoded the instruction . • everything instruction (opcode)-dependent from here on . Monday, February 4, 13

  24. 3. Execution, Memory Address Computation, or Branch Completion • Memory reference (load or store) • ALUOut = A + sign-extend(IR[15-0]) • R-type • ALUout = A op B • Branch • if (A == B) PC = ALUOut At this point, Branch is complete, and we start over; others require more cycles. Monday, February 4, 13

  25. 4. Memory access or R-type completion • Memory reference (load or store) • Load • MDR = Mem[ALUout] • Store • Mem[ALUout] = B • R-type • Reg[IR[15-11]] = ALUout R-type is complete, store is complete. Monday, February 4, 13

  26. 5. Memory Write-Back Reg[IR[20-16]] = MDR load is complete Monday, February 4, 13

  27. Summary of Execution Steps Step R-type Memory Branch Instruction Fetch IR = Mem[PC] PC = PC + 4 Instruction Decode/ A = Reg[IR[25-21]] register fetch B = Reg[IR[20-16]] ALUout = PC + (sign-extend(IR[15-0]) << 2) Execution, address ALUout = A op B ALUout = A + if (A==B) then computation, branch sign- PC=ALUout completion extend(IR[15-0]) Memory access or R- Reg[IR[15-11]] = memory-data = type completion ALUout Mem[ALUout] or Mem[ALUout]= B Write-back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  28. Complete Multi-Cycle Datapath Monday, February 4, 13

  29. Complete Multi-Cycle Datapath New Instruction Appears Out of Nowhere? Which One? Monday, February 4, 13

  30. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  31. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  32. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  33. 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Monday, February 4, 13

  34. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  35. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  36. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  37. 2. Instruction Decode and Register Fetch A = Register[IR[25-21]] B = Register[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Monday, February 4, 13

  38. 3. Execution (R-Type) ALUout = A op B Monday, February 4, 13

  39. 3. Execution (R-Type) ALUout = A op B Monday, February 4, 13

  40. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  41. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  42. 4. R-Type Completion Reg[IR[15-11]] = ALUout Monday, February 4, 13

  43. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  44. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  45. 3. Branch Completion if (A == B) PC = ALUOut Monday, February 4, 13

  46. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  47. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  48. 4. Memory Address Computation ALUout = A + sign-extend(IR[15-0]) Monday, February 4, 13

  49. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  50. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  51. 4. Memory Access Load memory-data = Memory[ALUout] Monday, February 4, 13

  52. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  53. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  54. 4. Memory Access Store Memory[ALUout] = B Monday, February 4, 13

  55. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  56. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  57. 5. Load Write-Back Reg[IR[20-16]] = memory-data Monday, February 4, 13

  58. 3. Jump Completion PC = PC[31-28] | (IR[25-0] <<2) Monday, February 4, 13

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