Moonsu Kim, Kyounghwan Lim and Cheoljun Bae Samsung Electronics Co., Ltd. System LSI Division
• Design Trend • According to advanced process node, - # of cells ↑, voltage ↓, random variation impact ↑ - Parametric yield loss becomes severer • Design method • Random variation for STA - Semi Statistical STA instead of full SSTA: POCV(Synopsys), SOCV(Cadence) - Statistical equation for timing path slack slack = u slack – K* σ slack Mean of slack Standard deviation of slack K: seed sigma - Industry standard: K =3 slack = 0 means 99.865% yield guarantee for a timing path 1/9
• Risk of seed sigma K =3 • Design size( or # of paths) increases, K=3 is enough? • # of paths increase, yield loss probability increases yield of a core block is either 99.865%, 97.7% or 84.1% yield of all timing paths in a core block is 99.865% • To maximize profit of mass product • Reduce parametric yield loss • Require Yield aware Design - Quick & accurate estimation method of parametric timing yield during design stage - Find an appropriate seed sigma(K) considering yield - Yield aware ECO 2/9
• Yield computation • A path yield(success probability) is computed using slack distribution • Slack distribution is converted to z-score (generally x=0) • Chip(block or core) yield: - Bin[i] have associated z-score range(criticality) and number of paths assigned to it - Assign each critical path to a bin based on z-score Compute yield of each bin compute yield of a chip Yield of chip Yield of paths Probability of # of paths in in bin[i] a path in bin[i] bin[i] 3/9
• Overall Flow • Input: semi SSTA based Design DB • Bin based yield estimation - Fast but accuracy loss due to assumption of independence between paths • MonteCalro based yield estimation - More accurate than bin-based but runtime/resource overhead 4/9
• Seed sigma (K) decision • During design plan, yield estimations for different K values • Find minimum K which satisfies target yield • Decided seed sigma value is used for remain STA & ECO for sign-off • Overall Flow 5/9
• Objective: fix minor violations to meet target yield • Input: criticality bin • Method (originally LP formula implemented as iterative greedy algorithm) • Phase1: Find new histogram by find X (= # of move from bin i to bin j) • Phase2: assign actual bin-to-bin move and realize timing ECO X i j i j Bin index Original bin New bin histogram Current yield Y < new yield Y’ If a path should move from bin i to bin j, apply ECO slack margin: 6/9
• Yield Estimation • Bin based yield estimation is practical than MC based • Runtime benefit with small accuracy loss (Table 3) • Yield aware ECO (Table 4) • Ref(Reference) - No target yield - Seed sigma: any higher value(ex. 3.5, 4.0…) than 3.0 - After all violations are fixed , expected yield is computed by bin based yield estimation flow • YaE (Yield aware ECO) - Target yield is set to expected yield of reference - Seed sigma : 3.0 - After complete Yield aware ECO to achieve target yield, expected yield is computed by bin based yield estimation flow Expected yield of YaE is very close to Ref’s with less runtime and # of △ buffer s - 7/9
• Comparison two Silicon data of two real projects • Silicon data: hold timing limited minimum voltage (Vmin) lower is better • Design 1 and Design2 - Both designs have common component (blockA, blockB, blockC) - blockA,B are small and blockC is big one(10X than A or B) - Design2’s lowest sign - off voltage < design1’s lowest sign -off voltage - Yield aware design is applied Design1 blockC only • Difficulty of apple-to-apple comparison There are many differences: design style, library cell, sign-off voltage affect Vmin result complexly - - Very difficult to separate them from yield aware design impact • In-direct comparison - Vmin @P50 of blockA, blockB: Design1 > Design2 (Design2 is better) Vmin @P50 of blockC: Design1 < Design2 (Design1 is better) yield aware design impact - - Spread of Vmin of blockA, blockB: Design1 is slightly better than Design2 Spread of Vmin of blockC: Design1 is much better than Design2 yield aware design impact - P50: 50% percentile Vmin of EDS test P90: 90% percentile Vmin of EDS test 8/9
• Considering design size and random variation impact on low voltage domain, seed sigma (K) of 3 may not be sufficient for mass product yield • We develop practical yield aware design flow • Yield estimation • Seed sigma decision flow • Yield aware ECO • Experimental results shows runtime/accuracy of proposed yield aware design flow • Silicon measurement data shows enhancement of Vmin by yield aware design 9/9
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