Mixed Gates: Leakage Reduction Mixed Gates: Leakage Reduction Techniques applied to Techniques applied to Switches for on- -chip Networks chip Networks Switches for on Frank Sill, Claas Cornelius, Stephan Kubisch, Dirk Timmermann Institute of Applied Microelectronics and Computer Engineering University of Rostock 1 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Focus of this Work Focus of this Work 1. Advancement of established Leakage Reduction techniques (DVTCMOS / DTOCMOS) 2. Application of the new approach to NOC Switches DVTCMOS: Dual V th CMOS DTOCMOS: Dual T ox CMOS NOC: Network-On-Chip 2 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Outline Outline 1. Motivation 2. Basics 3. Mixed Gates 4. Leakage Reduction of NOC Switches 5. Conclusion 3 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Motivation Motivation S. Borkar, ‘05 4 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Motivation Motivation Up to 50 % will be leakage! SiO2 Lkg - Gate Oxide Tunneling Leakage ( I gate ) SD Lkg - Subthreshold Leakage ( I sub ) S. Borkar, ‘05 5 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
2. Basics 2. Basics 6 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Power Dissipation in CMOS Power Dissipation in CMOS Gate I gate VDD Source Drain I gate SiO 2 I sub n + n + I dyn I sc I sub p - well L C L - I sub occurs if Vg < Vt - carriers move by diffusion along surface GND - I gate caused by direct tunneling through gate oxide 7 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
V th vs. Delay and Leakage V th vs. Delay and Leakage Inverter (BPTM 65 nm) 160 n 55 p Subthreshold Delay 50 p Leakage [A] 120 n Leakage Delay [s] 45 p 80 n 40 p 40 n 35 p 0 n 30 p 250 m 270 m 290 m 310 m 330 m 350 m 370 m Threshold Voltage Vth NMOS [V] 8 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
V th vs. Delay and Leakage V th vs. Delay and Leakage Inverter (BPTM 65 nm) 160 n 55 p Subthreshold fast devices with high power dissipation (low V th ) Delay 50 p Leakage [A] 120 n Leakage Delay [s] or 45 p 80 n 40 p slow devices with low power dissipation (high V th ) 40 n 35 p 0 n 30 p 250 m 270 m 290 m 310 m 330 m 350 m 370 m Threshold Voltage Vth NMOS [V] 9 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
T ox vs. Delay and Leakage T ox vs. Delay and Leakage Inverter (BPTM 65 nm) 160 n 50 p Gate- Delay Leakage [A] 45 p 120 n Delay [s] Leakage 40 p 80 n 35 p 40 n 30 p 0 n 25 p 14 16 17 18 20 22 Thickness of gate oxide (Tox) [10 -10 m] 10 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
T ox vs. Delay and Leakage T ox vs. Delay and Leakage Inverter (BPTM 65 nm) 160 n 50 p fast devices with high power dissipation (low T ox ) Gate- Delay Leakage [A] 45 p 120 n Delay [s] Leakage 40 p or 80 n 35 p slow devices with low power dissipation (high T ox ) 40 n 30 p 0 n 25 p 14 16 17 18 20 22 Thickness of gate oxide (Tox) [10 -10 m] 11 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
DVTCMOS / DTOCMOS DVTCMOS / DTOCMOS Dual Threshold Voltages (DVTCMOS) • Use different V th ’s – use lower threshold for devices within the critical paths – use higher threshold for devices outside the critical paths Dual Tox (DTOCMOS) • Use different T ox ’s – use thinner gate oxide for devices within the critical paths – use thicker gate oxide for devices outside the critical paths Decrease leakage without performance penalty 12 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
DVTCMOS / DTOCMOS cont’ ’d d DVTCMOS / DTOCMOS cont critical path LVTO (low V th / T ox = fast, high leakage) HVTO (high V th / T ox = slow, low leakage) 13 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
3. Mixed Gates 3. Mixed Gates 14 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Mixed- -V V th /T ox Pull- - Down/Up Down/Up - -Paths Paths Mixed th /T ox Pull Goal (for fast gates) : Preserve the delay while decreasing the leakage VDD 0 → 1 delay R (Output from GND to VDD) IN1 OUT IN2 1 → 0 delay (Output from VDD to GND) 2R delay 0 → 1 < delay 1 → 0 GND But : At timing analysis → only maximum delay is considered! 15 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Mixed- -V V th /T ox Pull- - Down/Up Down/Up - -Paths Cont Paths Cont’ ’d d Mixed th /T ox Pull Idea: Use different V th / T ox devices within a gate to adapt the delays 16 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Mixed- -V V th /T ox Pull- - Down/Up Down/Up - -Paths Cont Paths Cont’ ’d d Mixed th /T ox Pull Idea: Use different V th / T ox devices within a gate to adapt the delays High - Vth/Tox delay 0 → 1 = delay 1 → 0 Low - Vth/Tox 17 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Mixed Gates Mixed Gates Goal: Additional gate types at constant mask count Only two gate types in DVTCMOS / DTOCMOS → Problem: More high leakage gates after optimization as needed to keep the delay High - Vth/Tox Idea: Mixed V th / T ox gates to increase the amount of possible gate types Low - Vth/Tox 18 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Mixed Gates - - NAND2 NAND2 Mixed Gates Low - Vth/Tox High - Vth/Tox LVTO gate F - MG gate MG gate HVTO gate - rise time is shorter - rise and fall time are - middle delay cell - maximum delay cell than fall time nearly the same - middle leakage - minimum leakage - minimum delay cell - minimum delay cell - very high leakage - high leakage 19 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
4. Leakage Reduction of 4. Leakage Reduction of NOC Switches NOC Switches 20 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Network- -on on- -Chip Chip Network 21 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Switch – – Architecture Architecture Switch Bus width 16 North- Port Gate-Count 1,937 Control West- East- (Arbiter, FF-Count 193 Port Port Switching) l a c Frequency 337.6 MHz o t r L o South- P Port P dyn 214.7 µW Resource 22 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Simulation Results Results Simulation Leakage Reduction 80% 60% 40% 20% 0% 1D-Switch 2x1D-Switch 2D-Switch c499 MG vs. LVTO MG vs. DVTO 23 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
5. Conclusion 5. Conclusion - Subthreshold current and gate oxide leakage dominate leakage power - Mixed Gates approach combines advantages of DVTCMOS and DTOCMOS at transistor and gate level - Average 83% (vs. LVTO) and 10% (vs. DVTO- CMOS) leakage reduction at constant delay 24 University of Rostock Institute of Applied Microelectronics and Computer Engineering MG & Switch, Sill (ReCoSoC‘06)
Recommend
More recommend
