MIPS Assembly 2 Lab Schedule Activities Assignments Due This - PowerPoint PPT Presentation

ì Computer Systems and Networks ECPE 170 – Jeff Shafer – University of the Pacific MIPS Assembly

2 Lab Schedule Activities Assignments Due This Week Lab 10 ì ì Due by Apr 12 th 5:00am MIPS discussion ì ì Practice problems ì Lab 11 ì (whiteboard) Due by Apr 19 th 5:00am ì Using the QtSPIM ì simulator Lab 12 ì Discuss available resources ì Due by May 3 rd 5:00am ì Computer Systems and Networks Spring 2017

3 Person of the Day – John Cocke Computer architecture pioneer ì “Father of RISC Architecture” ì Developed IBM 801 processor, ì 1975-1980 Winner, ACM Turing Award , 1987 ì RISC = Reduced Instruction Set Computing Achieve higher performance with simple instructions that execute faster Computer Systems and Networks Spring 2017

4 Person of the Day – John Hennessy Computer architecture pioneer ì Popularized RISC architecture in early ì 1980’s Founder of MIPS Computer Systems ì in 1984 Currently president of an obscure ì school: Stanford University Computer Systems and Networks Spring 2017

5 Class to Date Human Compiler Compiler Linker (C Code) (Assembly (Object file / (Executable code) binary code) program) Computer Systems and Networks Spring 2017

6 Class Now Human Assembler Linker (Assembly (Object file / (Executable code) binary code) Program) Computer Systems and Networks Spring 2017

7 ì MIPS Computer Systems and Networks Spring 2017

8 MIPS Overview ì Family of computer processors first introduced in 1981 ì M icroprocessor without I nterlocked P ipeline S tages Original acronym ì Now MIPS stands for nothing at all… ì Computer Systems and Networks Spring 2017

9 MIPS Products Embedded devices ì Cisco/Linksys routers ì Cable boxes ì MIPS processor is buried inside System-on-a-Chip (SOC) ì Gaming / entertainment ì Nintendo 64 ì Playstation, Playstation 2, PSP ì Computers? ì Not so much anymore… ì SGI / DEC / NEC workstations back in 1990’s ì Computer Systems and Networks Spring 2017

10 MIPS Products NASA New Horizons probe ì Launched January 2006 ì MIPS “Mongoose-V” chip ì 12 MhZ ì (2006, remember?) Radiation Hardened ì Based on R3000 ì (PlayStation CPU) http://blog.imgtec.com/mips-processors/mips-goes-to-pluto http://synova.com/proc/MongooseV.pdf Computer Systems and Networks Spring 2017

11 MIPS Design ì RISC – What does this mean? R educed I nstruction S et C omputing ì Simplified design for instructions ì Use more instructions to accomplish same task ì ì But each instruction runs much faster! ì 32 bits (originally) – What does this mean? 1 “word”= 32 bits ì Size of data processed by an integer add instruction ì New(er) MIPS64 design is 64 bits, but we won’t ì focus on that Computer Systems and Networks Spring 2017

12 ì MIPS Assembly Programming Computer Systems and Networks Spring 2017

13 Quotes – Donald Knuth “People who are more than casually interested in computers should have at least some idea of what the underlying hardware is like . Otherwise the programs they write will be pretty weird.” – Donald Knuth This is your motivation in the assembly labs! Computer Systems and Networks Spring 2017

14 Why Learn Assembly Programming? Computer Science track ì Understand capabilities (and limitations) of physical ì machine Ability to optimize program performance (or ì functionality) at the assembly level if necessary Computer Engineer track ì Future courses (e.g. ECPE 173) will focus on processor ì design Start at the assembly programming level and move into ì hardware ì How does the processor implement the add instruction? ì How does the processor know what data to process? Computer Systems and Networks Spring 2017

15 Instruction Set Architecture ì Instruction Set Architecture (ISA) is the interface between hardware and software Specifies the format of processor instructions ì Specifies the format of memory addresses ì (and addressing modes) Specifies the primitive operations the processor can ì perform Computer Systems and Networks Spring 2017

16 Instruction Set Architecture ì ISA is the “contract” between the hardware designer and the assembly-level programmer ì Documented in a manual that can be hundreds or thousands of pages long Example: Intel 64 and IA-32 Architectures Software ì Developers Manual http://www.intel.com/content/www/us/en/process ì ors/architectures-software-developer-manuals.html No joke – the manual PDF from December 2015 ì is 3883 pages long ! Computer Systems and Networks Spring 2017

17 Instruction Set Architecture ì Processor families share the same ISA ì Example ISAs: Intel x86 ì Intel / AMD x86-64 ì All completely different, Intel Itanium in the way that C++, Java, ì Perl, and PHP are all ARM ì different… IBM PowerPC ì MIPS ì … and yet learning one language makes learning the next one much easier Computer Systems and Networks Spring 2017

18 Why MIPS? ì Why choose MIPS? The MIPS ISA manual (volume 1, at least) is a svelte ì 108 pages ! Extremely common ISA in textbooks ì Freely available simulator ì Common embedded processor ì Good building-block for other RISC-style processors ì Aligns with ECPE 173 course ì Computer Systems and Networks Spring 2017

19 Arithmetic Instructions ì Addition add <result>, <input1>, <input2> ì Subtraction sub <result>, <input1>, <input2> Operation / “Op code” Operands Computer Systems and Networks Spring 2017

20 Task : Write Code ì Write MIPS assembly for f = (g+h) – (i+j) add temp0, g, h add temp1, i, j sub f, temp0, temp1 Computer Systems and Networks Spring 2017

21 Congratulations! You’re now an assembly programming expert! Computer Systems and Networks Spring 2017

22 Data Sources ì Previous example was (just a little bit) fake… We made up some variables: ì temp0 , temp1 , f , g , h , i , and j This is what you do when programming in C++ ì (or any high level language) Problem: You can’t make up variables in assembly! (as least, not in this fashion) Computer Systems and Networks Spring 2017

23 Data Sources Where can we explicitly place data in assembly programming? Registers 1. On the CPU itself CPU ì Very close to ALU ì Tiny ì Access time: 1 cycle ì ALU Cache Memory Memory 2. Off-chip ì Large ì Access time: 100+ cycles ì Computer Systems and Networks Spring 2017

24 Aside – Cache ì Review: Does the programmer explicitly manage the cache? ì Answer: No! The assembly programmer just reads/writes ì memory addresses Cache is managed automatically in hardware ì Result: Memory appears to be faster than it really is ì Computer Systems and Networks Spring 2017

25 ECPE 71 ì From your knowledge of ECPE 71 (Digital Design), how would you construct a register? Flip Flops! (D Flip Flop shown) Computer Systems and Networks Spring 2017

26 ECPE 71 – Group of Registers Computer Systems and Networks Spring 2017

27 Registers MIPS design: 32 integer registers , each holding 32 bits ì “Word size” = 32 bits ì Name Use Constant value: ZERO $zero Local variables $s0-$s7 Temporary results $t0-$t9 This is only 19 – where are the rest of the 32? ì Reserved by convention for other uses ì We’ll learn a few more later… ì Computer Systems and Networks Spring 2017

28 Task : Write Code ì Write MIPS assembly using registers for: f = (g+h) – (i+j) Code: Map: $s0 = g add $t0, $s0, $s1 $s1 = h add $t1, $s2, $s3 $s2 = i sub $s4, $t0, $t1 $s3 = j $s4 = f Computer Systems and Networks Spring 2017

29 More Arithmetic Instructions ì Add Immediate addi <result>, <input1>, <constant> Register Register Can be a positive or negative number! Computer Systems and Networks Spring 2017

30 Task : Write Code ì Write MIPS assembly using registers for: f = g+20 Code: Map: addi $s0, $s1, 20 $s0 = f $s1 = g Computer Systems and Networks Spring 2017

31 Memory ì Challenge: Limited supply of registers Physical limitation: We can’t put more on the ì processor chip, and maintain their current speed Many elements compete for space in the CPU… ì ì Solution: Store data in memory ì MIPS provides instructions that transfer data between memory and registers Computer Systems and Networks Spring 2017

32 Memory Fundamentals MIPS cannot directly manipulate data in memory! Data must be moved to a register first! (And results must be saved to a register when finished) This is a common design in RISC-style machines: a load-store architecture Computer Systems and Networks Spring 2017

33 Memory Fundamentals Yes, it’s a pain to keep moving data between registers and memory. But consider it your motivation to reduce the number of memory accesses. That will improve program performance ! Computer Systems and Networks Spring 2017

34 Memory Fundamentals ì Four questions to ask when accessing memory: What direction do I want to copy data? 1. (i.e. to memory, or from memory?) What is the specific memory address ? 2. What is the specific register name ? (or number) 3. How much data do I want to move? 4. Computer Systems and Networks Spring 2017