Memory Systems Solid State Disks Anwar,Hossameldin Department of - PowerPoint PPT Presentation

IEE5008 – Autumn 2012 Memory Systems Solid State Disks Anwar,Hossameldin Department of Electronics Engineering National Chiao Tung University Eng_hossam123@yahoo.com Anwar,Hossameldin 2012

Outline  Introduction  Flash memory  Flash Translation Layer (FTL)  Solid-State Disks (SSDs)  Hydra Solid-State Disk Architecture  Hydra SSD Architecture Key Features and Techniques  Performance Evaluation (PC MARK05)  Related Issues  Conclusion  References Anwar,Hossameldin 2

Introduction  Flash memory enabled devices such as MP3 players, mobile phones, digital cameras are widely used todays.  Flash memory features: 1 .Low power consumption. 2 .Nonvolatility. 3 .High random access performance. 4 .High mobility.  Solid-State Disks(SSDs) are composed of multiple NAND flash memory chips, replacing HDDs in the mass storage market.  Solid-State Disks(SSDs) features: 1 .Low power consumption. 2 .Faster random access. 3 .Greater shock resistance.  SSD performance is being increased due to the exploitation of parallel I/O architectures. Anwar,Hossameldin 3

 An SSD interacts with the host computer via standard interface such as PATA or SATA and behaves much like a standard hard drive.  O perating systems use storage devices to provide file systems and virtual memory.  Flash transfer layer (FTL) is a software layer, used to emulate the functionality of HDDs.  It hides the peculiarities of flash memory and gives the illusion of an HDD.  SSD challenges: 1 .Reliability for large scale flash storage. 2 .The balance between cost, performance and lifetime. 3 .Cost per bit of NAND flash memory is still high.  Hydra SSD Architecture is our proposed solution to enhance storage system performance using the parallelism of multiple NAND flash memory chips.  T here are various techniques to achieve this goal: 1 .Bus-level and Chip-level interleaving for flash memory buses. • Problem : T he difference between the slow flash memory bus(<40MB/s) and the host interface(>150MB/s). • Result : T he collective bandwidth meets or exceeds that of the host interface. I t hides the flash memory latency. Anwar,Hossameldin 4

2 .Multiple High-level flash memory controllers. • I t executes sequences of high-level flash memory operation without intervention by FTL. • I t divides as two units of controllers (foreground unit and background unit). • T he foreground unit has priority over the background unit and it used to expedite the processing of host read requests. 3 .The write buffering. • I t expedites the processing of host write requests. • I t allows the parallelism in multiple flash memory chips to be exploited by multiple background units. • S o, it performs materialization to flash memory in parallel on different interleaved units Anwar,Hossameldin 5

Flash Memory  A NAND flash memory chip consist of a set of blocks.  Each block consists of a set of pages.  Each page has two parts: D ata part that stores the user data. • S pare part that stores metadat that associated with the user data. •  The size of the data part is a multiple of the sector size(512 bytes).  The size of the spare part is 16 bytes for each sector in the data part.  Currently, the most popular block size is 128 KB, consisting of 64 pages, each of 2 KB (a data part of four sectors and a spare part of 64 bytes).  Flash memory has several features, unlike the traditional magnetic hard disk. 1 .”Erase before Write” Architecture • The block should be first cleaned by the erase command to write data into this block. 2 .The unit size of the erase and write operations are symmetric. The write operation is performed by the unit of a page. • Flash translation layer(FTL) software is required to map the logical page address from the • host system to the physical page address in the flash memory devices. Anwar,Hossameldin 6

 There are four major operations provided by typical low-level flash memory controller: Erase Block Operation Program Page Operation Read Page Operation Copy-Back Page Operation Anwar,Hossameldin 7

 The erase block operation • It sets all the bits in a block to 1 and takes about 2 ms. • It is initiated by an erase command that includes the address of the block to be erased. After the erase complete, status check command is issued to detect any errors during the • operations.  The program page operation It writes the data supplied to the page(previously erased). • • It consists of three phase: 1 .Data transfer phase, data to be written to the target page is transferred at 40 MB/s over the flash memory bus to the internal page buffer in the NAND flash memory chip. 2 .Program command is issued along with address of the target page (takes about 200 us). 3 .After program operation is complete, a status check command is issued to check for errors. Anwar,Hossameldin 8

 The read page operation • It reads a page from flash memory 1 .Read command is issued. 2 .This loads a page into the memory’s internal page buffer (takes about~20 us). 3 .The data in the internal page buffer is read out at 40 MB/s over the flash memory bus.  The copy-back page operation • It transfers data from one page into another inside the chip. • It is more efficient that moving the data out of the chip and back in again. It uses read page operation followed by a program page operation • 1 .It is initialed by a read command that moves the data to the internal page buffer. 2 .The data corresponding to the portion of the page to be modified is transferred to the internal page buffer and the program command is issued. 3 .finally, the usual status check is performed. Anwar,Hossameldin 9

Flash Transfer Layer (FTL)  It hides the peculiarities of flash memory and emulates the functionality of an HDD.  It maintains a mapping between the logical sector address used by the host system and the physical flash memory address.  The address mapping schemes of the FTL can be divided into three classes. Page-level mapping Block-level mapping Hybrid mapping Anwar,Hossameldin 10

 Page-Level Mapping • It used to map a logical page to any physical page in flash memory. • When the host sends the read request with a logical page number(LPN),FTL finds the physical page number(PPN) from the mapping table. Since the mapping table is generally maintained in SRAM,each physical page has its LPN in • the spare field against sudden power failure. If the update request is sent for the data that have been already written to the flash memory, • page-level mapping techniques writes the new data to an empty page, invalidates the old data and changes the mapping information for the logical page number. That’s because the flash memory page can not be overwritten. • • The invalidation of old data is marked at its spare field. • The disadvantage of this technique : it requires a large SRAM for mapping table. Anwar,Hossameldin 11

 Block-Level Mapping • Only mapping information between the logical block number(LBN) and the physical block number(PBN) is maintained. • A page should be in the same page offset within both the logical block and the physical block. It requires small-sized mapping table. • However, when the logical page is updated, the page should be written to new clean flash • block. So, all of non updated pages of the old block should be copied into the new flash block. • • It invokes large page migration costs. Anwar,Hossameldin 12

 Hybrid Mapping • It is a comprise between page-level mapping and block-level mapping. A small portion of physical block is reserved as a log buffer. • While the log blocks in the log buffer use the page-level mapping scheme, the normal data • blocks are handled by the block-level mapping. When a write request is sent to the FTL, the data are written to a log block, and the • corresponding old data in the data block are invalidated. • When there is no empty space in the log buffer, one of the log blocks is selected as a victim and all of the valid pages in the log block are moved into the data blocks to make space for on-going write requests. • Hybrid mapping requires a small-sized mapping table since only the log blocks are handled by the page-level mapping. Anwar,Hossameldin 13

Solid-State Disks(SSDs)  A typical SSD is composed of host interface control logic , an array of NAND flash memory , RAM and SSD controller .  The host transfer control logic transfers command data from/to the host via the USB, PATA, protocol.  SSD controller is used to translate read/write requests into flash memory operations.  The controller exploits RAM to temporarily buffer write requests or accessed data during handling read/write requests.  The entire operations are governed by firmware(FTL),run by the SSD controller. Anwar,Hossameldin 14

 To increase the read/write bandwidth of SSD,many SSDs use an interleaving technique that exploits the parallelism of accessing multiple NAND chips simultaneously.  If there are multiple independent channels, the read/write bandwidth of SSDs can be accelerated further by exploiting interchannel and intrachannel parallelism.  Example : Write or Program operation steps: 1 .Loading data to the internal page register of a NAND chip. 2 .Programming the loaded data into the appropriate NAND flash cells.  So, data can be loaded to another NAND chip during the data programming time.  That’s because the data programming time is longer than the data loading time. Anwar,Hossameldin 15