Memory Devices Small: Register file (group of numbered registers) Medium: SRAM (Static Random Access Memory) Large: DRAM (Dynamic Random Access Memory) Future? 1
Processor: Data Path Components 1 3 2 Instruction ALU Registers Memory Fetch and Decode
SRAM: Static Random Access Memory Address 21 Chip select 16 SRAM Output enable Dout[15–0] 2M 3 16 Write enable Din[15–0] 16 3
SRAM read port: data out Large register files are impractical. Big MUX = significant gate delay. Large memories use a shared output line. No central gates/MUX to choose output! 5
Wired ORs (don't try this at home/in the lab, kids) Danger, Will Robinson! 6
(noninverting) tristate buffers Out In Control In Control Out 0 0 Z 1 0 Z 0 1 0 1 1 1 (active high) 7
SRAM cell one option Tristate Buffer Data In D Q D Latch Data Out Clock C Q Enable 8
Data in: D in [1] D in [0] Din[1] Din[1] SRAM write port: D D D D C Q C Q latch latch Write enable Write enable Enable Enable 0 0 Address 2-to-4 D D D D decoder C Q C Q latch latch Enable Enable 1 2-to-4 decoder 1 D D D in [i] D out [i] D D C Q C Q Address latch latch Enable Enable D 2 D 2 C Q latch D D D D Enable C Q C Q latch latch Enable Enable Address 3 3 select Write enable D out [1] Data out: D out [0] Dout[1] Dout[0]
Organization of a 16 x 4 SRAM (one option) 4-bit address 4 to 16 decoder data out 10
Selecting location 1101 4-bit address 1101 4 to 16 decoder data out 11
Another organization of a 16 x 4 SRAM Split-level row/column addressing = physical multidimensional array! top 2 bits (row) address 2 to 4 decoder bottom 2 bits address Mux Mux Mux Mux (column) Notice the smaller decoder... how does this affect timing? 12
Selecting location 0010 Nibbles "striped" across 4 smaller memories. top 2 bits (row) address 2 to 4 decoder 00 10 2 2 bottom 2 bits address Mux Mux Mux Mux 4 (column) 0010 13
Selecting location 1101 Nibbles "striped" across 4 smaller memories. top 2 bits (row) address 2 to 4 decoder 11 01 2 2 bottom 2 bits address Mux Mux Mux Mux 4 (column) 1101 14
What value does location 1010 hold? 0 1 1 1 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 2 to 4 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1 decoder 0 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 2 2 Mux Mux Mux Mux 4 1010 15
Organization of a 4M x 8 SRAM (one option) = 4 MB memory, size of a large cache for modern laptop 4K � 4K � 4K � 4K � 4K � 4K � 4K � 4K � 1024 1024 1024 1024 1024 1024 1024 1024 SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM 12 4096 Address to [21–10] 4096 decoder 1024 Address [9–0] Mux Mux Mux Mux Mux Mux Mux Mux Dout7 Dout6 Dout5 Dout4 Dout3 Dout2 Dout1 Dout0 In practice, single set of data lines often time-shared for read (out)/write (in). 16
Word line Pass transistor Capacitor Dynamic RAM = DRAM Bit line DRAM stores bit as charge on capacitor: • 1 transistor accesses stored charge. • requires periodic refresh = read-write (dynamic power) SRAM stores bit on pair of inverting gates: • several transistors • requires continuous (static) power. 17
DRAM design (one option) Row 2048 � 2048 decoder array 11-to-2048 Address[10–0] Column latches Single set of address lines, time-shared for row address, column address. Mux Accesses entire row, stores in column latches. Mainly used for refreshing entire row at a time. Dout Accessing other columns in same row again cheaper...? 18
64-bit DRAM 3 to 8 row decoder 3-bit Column latches address Mux Data out 19
Reading bit at address 101011 1. Select row 3 to 8 row decoder 101 Column latches 3-bit address Mux Data out 20
Reading bit at address 101011 2. Copy row to latches 3 to 8 row decoder Row is fading! 101 Column latches 3-bit address Mux Data out 21
Reading bit at address 101011 3. Refresh row from latches 3 to 8 row decoder Refresh. 101 Column latches 3-bit address Mux Data out 22
Reading bit at address 101011 4. Select column from latches 3 to 8 row decoder 011 Column latches 3-bit address Mux Data out 23
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