MARACAS Ying Ye, Richard West, MARACAS: A Real-Time Multicore VCPU Jingyi Zhang, Zhuoqun Cheng Scheduling Framework Introduction Quest RTOS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Background Scheduling Memory- Computer Science Department Aware Scheduling Boston University Multicore VCPU Scheduling Evaluation Conclusion
Overview MARACAS Ying Ye, Introduction 1 Richard West, Jingyi Zhang, Zhuoqun Cheng Quest RTOS 2 Introduction Background Scheduling 3 Quest RTOS Background Scheduling Memory-Aware Scheduling 4 Memory- Aware Scheduling Multicore VCPU Scheduling 5 Multicore VCPU Scheduling Evaluation 6 Evaluation Conclusion Conclusion 7
Motivation MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Multicore platforms are gaining popularity in embedded Cheng and real-time systems Introduction concurrent workload support Quest RTOS less circuit area Background lower power consumption Scheduling lower cost Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Motivation MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Multicore platforms are gaining popularity in embedded Cheng and real-time systems Introduction concurrent workload support Quest RTOS less circuit area Background lower power consumption Scheduling lower cost Memory- Aware Scheduling Multicore Complex on-chip memory hierarchies pose significant VCPU Scheduling challenges for applications with real-time requirements Evaluation Conclusion
Motivation MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Shared cache contention: page coloring Introduction hardware cache partitioning (Intel CAT) Quest RTOS static VS dynamic Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Motivation MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Shared cache contention: page coloring Introduction hardware cache partitioning (Intel CAT) Quest RTOS static VS dynamic Background Scheduling Memory- Memory bus contention: Aware Scheduling bank-aware memory management Multicore memory throttling VCPU Scheduling Evaluation Conclusion
Contribution MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng We proposed the use of foreground (reservation) + background (surplus) scheduling model Introduction improves application performance Quest RTOS effectively reduces resource contention Background Scheduling well-integrated with real-time scheduling algorithms Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Contribution MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng We proposed the use of foreground (reservation) + background (surplus) scheduling model Introduction improves application performance Quest RTOS effectively reduces resource contention Background Scheduling well-integrated with real-time scheduling algorithms Memory- Aware Scheduling We proposed a new bus monitoring metric that accurately Multicore VCPU detects traffic Scheduling Evaluation Conclusion
Application MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Imprecise computation/Numeric integration MPEG video decoding: mandatory to process I-frames, Introduction optional to process B- and P-frames to improve frame rate Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Application MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Imprecise computation/Numeric integration MPEG video decoding: mandatory to process I-frames, Introduction optional to process B- and P-frames to improve frame rate Quest RTOS Background Scheduling Mixed-criticality systems running performance-demanding Memory- Aware applications Scheduling machine learning Multicore VCPU computer vision Scheduling Evaluation Conclusion
Quest RTOS MARACAS Ying Ye, Richard West, VCPU model (C, T) in Jingyi Zhang, Zhuoqun Quest RTOS Cheng C: Capacity Introduction T: Period Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Quest RTOS MARACAS Ying Ye, Richard West, VCPU model (C, T) in Jingyi Zhang, Zhuoqun Quest RTOS Cheng C: Capacity Introduction T: Period Quest RTOS Background Scheduling Partitioned scheduling Memory- using RMS Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Quest RTOS MARACAS Ying Ye, Richard West, VCPU model (C, T) in Jingyi Zhang, Zhuoqun Quest RTOS Cheng C: Capacity Introduction T: Period Quest RTOS Background Scheduling Partitioned scheduling Memory- using RMS Aware Scheduling Multicore VCPU Schedulability test √ Scheduling � n 1 ( C i n T i ) ≤ n ( 2 − 1) Evaluation Conclusion
Background Scheduling MARACAS Ying Ye, VCPU enters background Richard West, Jingyi Zhang, mode upon depleting its Zhuoqun Cheng budget (C) Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Background Scheduling MARACAS Ying Ye, VCPU enters background Richard West, Jingyi Zhang, mode upon depleting its Zhuoqun Cheng budget (C) Introduction Quest RTOS Core enters background mode when all VCPUs are in Background background mode Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Background Scheduling MARACAS Ying Ye, VCPU enters background Richard West, Jingyi Zhang, mode upon depleting its Zhuoqun Cheng budget (C) Introduction Quest RTOS Core enters background mode when all VCPUs are in Background background mode Scheduling Memory- Aware Scheduling Background CPU Time ( BGT ): time a VCPU runs when Multicore core in background mode VCPU Scheduling Evaluation Conclusion
Background Scheduling MARACAS Ying Ye, VCPU enters background Richard West, Jingyi Zhang, mode upon depleting its Zhuoqun Cheng budget (C) Introduction Quest RTOS Core enters background mode when all VCPUs are in Background background mode Scheduling Memory- Aware Scheduling Background CPU Time ( BGT ): time a VCPU runs when Multicore core in background mode VCPU Scheduling Evaluation Background scheduling: schedule VCPUs when core is in Conclusion background mode fair share of BGT amongst VCPUs on core
DRAM structure MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Memory-Aware Scheduling MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Prior work [MemGuard] uses ”Rate Metric”: Introduction number of DRAM accesses over a certain period Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Memory-Aware Scheduling MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Prior work [MemGuard] uses ”Rate Metric”: Introduction number of DRAM accesses over a certain period Quest RTOS Background Bank-level parallelism Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Memory-Aware Scheduling MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Prior work [MemGuard] uses ”Rate Metric”: Introduction number of DRAM accesses over a certain period Quest RTOS Background Bank-level parallelism Scheduling Row buffers Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Memory-Aware Scheduling MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Prior work [MemGuard] uses ”Rate Metric”: Introduction number of DRAM accesses over a certain period Quest RTOS Background Bank-level parallelism Scheduling Row buffers Memory- Aware Sync Effect Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Sync Effect MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Sync Effect MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling Each task reduces its access rate by a factor of (T-t)/T Evaluation Conclusion Contention in [0, t] remains the same
Latency Metric MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling requests = 3 , occupancy = 10 Evaluation Conclusion
Latency Metric MARACAS Ying Ye, Richard West, Jingyi Zhang, Zhuoqun Cheng Introduction Quest RTOS Background Scheduling Memory- Aware Scheduling Multicore VCPU Scheduling requests = 3 , occupancy = 10 Evaluation latency = 10 3 = 3 . 3 Conclusion
Latency Metric MARACAS Ying Ye, Richard West, Jingyi Zhang, UNC ARB TRK REQUEST.ALL ( requests ): Zhuoqun Cheng counts all memory requests going to the memory controller request queue Introduction Quest RTOS Background UNC ARB TRK OCCUPANCY.ALL ( occupancy ): Scheduling counts cycles weighted by the number of pending requests Memory- Aware in the queue Scheduling Multicore VCPU Scheduling Evaluation Conclusion
Recommend
More recommend
