Main Memory: Address Translation (Chapter 12-17) CS 4410 Operating Systems
Can’t We All Just Get Along? Physical Reality: different processes/threads share the same hardware à need to multiplex • CPU (temporal) • Memory (spatial) • Disk and devices (later) Why worry about memory sharing? • Complete working state of process and/or kernel is defined by its data (memory, registers, disk) • Don’t want different processes to have access to each other’s memory (protection) 2
Aspects of Memory Multiplexing Isolation Don’t want distinct process states collided in physical memory (unintended overlap à chaos) Sharing Want option to overlap when desired (for efficiency and communication) Virtualization Want to create the illusion of more resources than exist in underlying physical system Utilization Want to best use of this limited resource 3
A Day in the Life of a Program Compiler Loader (+ Assembler + Linker) “It’s alive!” sum pid xxx sum.c process executable source PC SP files 0xffffffff ... stack #include <stdio.h> 0040 0000 0C40023C 21035000 main int max = 10; .text 1b80050c int main () { 8C048004 heap int i; 21047002 int sum = 0; 0C400020 data add(m, &sum); ... max printf(“%d”,i); 0x10000000 1000 0000 10201000 ... 21040330 .data text max 22500102 jal } addi ... 0x00400000 4 0x00000000
Virtual view of process memory 0xffffffff stack heap data text 0x00000000 5
TERMINOLOGY ALERT: Paged Translation Page: virtual Frame: physical Process View Virtual Page N Physical stack Memory No more Frame M STACK 0 external HEAP 0 fragmentation! TEXT 1 heap HEAP 1 DATA 0 TEXT 0 data STACK 1 text Frame 0 Virtual Page 0 6
Paging Overview Divide: • Physical memory into fixed-sized blocks called frames • Virtual memory into blocks of same size called pages Management: • Keep track of which pages are mapped to which frames • Keep track of all free frames Notice: • Not all pages may be mapped to frames 7
Address Translation, Conceptually Virtual Address Raise Invalid Processor Translation Exception ? s i h t s e o Valid d o h W Physical Memory Data Physical Address Data 8
Memory Management Unit (MMU) • Hardware device • Maps virtual to physical address (used to access data) User Process: • deals with virtual addresses • Never sees the physical address Physical Memory: • deals with physical addresses • Never sees the virtual address 9
High-Level Address Translation Process Physical View Memory red cube is 255 th Page N Frame M byte in page 2. stack STACK 0 HEAP 0 Where is the red cube TEXT 1 heap in physical memory? HEAP 1 DATA 0 data TEXT 0 text STACK 1 Page 0 Frame 0 10
Virtual Address Components Page number – Upper bits • Must be translated into a physical frame number Page offset – Lower bits • Does not change in translation page offset page number m - n n For given logical address space 2 m and page size 2 n 11
High-Level Address Translation Virtual Physical Who keeps Memory Memory track of the mapping? stack STACK 0 HEAP 0 0x???? TEXT 1 heap 0x6000 à Page Table HEAP 1 0x5000 0x5000 0 - DATA 0 0x4000 data 0x4000 1 3 TEXT 0 0x3000 0x3000 0x20FF 2 6 text 0x2000 0x2000 3 4 STACK 1 0x1000 0x1000 4 8 0x0000 5… 5 0x0000 12
Simple Page Table Page-table Lives in Memory Page-table base register (PTBR) • Points to the page table • Saved/restored on context switch PTBR 13
Leveraging Paging • Protection • Demand Loading • Copy-On-Write 14
Full Page Table Page-table Meta Data about each frame Protection R/W/X, Modified, Valid, etc. MMU Enforces R/W/X protection (illegal access throws a page fault) PTBR 15
Leveraging Paging • Protection • Demand Loading • Copy-On-Write 16
Demand Loading • Page not mapped until it is used • Requires free frame allocation • What if there is no free frame??? • May involve reading page contents from disk or over the network 17
Leveraging Paging • Protection • Demand Loading • Copy-On-Write (or fork() for free) 18
Copy on Write (COW) Physical P1 Virt Addr Space Addr Space COW X stack • P1 forks() X heap heap • P2 created with X data text - own page table text X - same translations P2 Virt Addr Space • All pages data X stack marked COW stack heap X (in Page Table) data X X text 19
Option 1: fork, then keep executing Physical P1 Virt Addr Space Addr Space COW X Now one process stack stack tries to write to the X heap heap stack (for example) : X data text • Page fault text X • Allocate new frame P2 Virt Addr Space • Copy page data X stack • Both pages no stack heap longer COW X data X X text 20
Option 2: fork, then call exec Physical P1 Virt Addr Space Addr Space COW Before P2 calls X stack exec() X heap heap X data text text X P2 Virt Addr Space P2 Virt Addr Space data X stack stack stack heap heap X data data X X text text 21
Option 2: fork, then call exec Physical P1 Virt Addr Space Addr Space COW stack stack After P2 calls heap heap exec() data text text text • Allocate new P2 Virt Addr Space data frames data stack • Load in new stack pages data • Pages no longer text COW 22
Problems with Paging Memory Consumption: • Internal Fragmentation • Make pages smaller? But then… • Page Table Space: consider 48-bit address space, 2KB page size, each PTE 8 bytes • How big is this page table? - Note: you need one for each process • How many pages in memory does it need? Performance: every data/instruction access requires two memory accesses: • One for the page table • One for the data/instruction 23
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 24
Multi-Level Page Tables to reduce page table space Implementation Physical Memory Processor Virtual Address index 1 | index 2 | offset Index 1 Index 2 Index 3 Offset Physical Address Level 1 Frame Offset Level 2 Frame Level 3 Frame | Access + Allocate only PTEs in use + Simple memory allocation − more lookups per memory reference 25
Two-Level Paging Example 32-bit machine, 1KB page size • Logical address is divided into: – a page offset of 10 bits (1024 = 2^10) – a page number of 22 bits (32-10) • Since the page table is paged, the page number is further divided into: – a 12-bit first index – a 10-bit second index • Thus, a logical address is as follows: page number page offset index 1 index 2 offset 12 10 10 26
This one goes to three levels! Implementation Physical Memory Processor Virtual Address Index 1 Index 2 Index 3 Offset Physical Address Level 1 Frame Offset Level 2 Level 3 + First Level requires less contiguous memory − even more lookups per memory reference 27
Complete Page Table Entry (PTE) Valid Protection R/W/X Ref Dirty Index Index is an index into: • frames - physical process memory or next level page table • backing store - if page was swapped out Synonyms: • Valid bit == Present bit • Dirty bit == Modified bit • Referenced bit == Accessed bit 28
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 29
Inverted Page Table: Motivation P4 So many virtual pages… virtual address P1 virtual space address space P2 virtual physical address P3 virtual address space space P5 virtual address space address space … comparatively few physical frames Traditional Page Tables: • map pages to frames 30 • are numerous and sparse
Inverted Page Table: Implementation Virtual address pid page # offset pid page Page-table Physical Memory page pid h c r a e g S n offset i h c t a m d r i p o F & e g a Implementation: p frame • 1 Page Table for entire system • 1 entry per frame in memory • Why don’t we store the frame #? 31 Not to scale! Page table << Memory
Inverted Page Table: Discussion Tradeoffs: ↓ memory to store page tables ↑ time to search page tables Solution: hashing • hash(page,pid) à PT entry (or chain of entries) • What about: • collisions… • sharing… 32
Address Translation • Paged Translation • Efficient Address Translation • Multi-Level Page Tables • Inverted Page Tables • TLBs 33
Translation Lookaside Buffer (TLB) Associative cache of virtual to physical Physical page translations Memory Virtual Address Page# Offset Translation Lookaside Buffer (TLB) Virtual Page Page Frame Access Physical Address Matching Entry Frame Offset Page Table 34 Lookup
Address Translation with TLB Access TLB before you access memory. Virtual Virtual Address Address Raise Miss Invalid Processor TLB Page Exception Table Hit Valid Frame Frame Offset Physical Memory Physical Address Data Trick: access TLB Data while you access the cache. 35
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