Memory Systems Design & Programming CMPE 310 Memory Address - PowerPoint PPT Presentation

Memory Systems Design & Programming CMPE 310 Memory Address Decoding The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is nec- essary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space. 1

Memory Systems Design & Programming CMPE 310 Memory Address Decoding A 0 O 0 A 1 O 1 Address Bus Data Bus ... ... A 19 A 10 O 7 A 18 2716 A 17 (2K X 8) A 16 EPROM A 15 CS A 14 A 13 A 12 A 11 RD of 8088/86 Or MRDC bus signal. IO/ M Logic 0 when A 11 through A 19 are all 1. (Book shows OE connection for RD but chip definition does NOT have this pin) 2

Memory Systems Design & Programming CMPE 310 Memory Address Decoding To determine the address range that a device is mapped into: A 19 - A 11 A 10 - A 0 1111 1111 1XXX XXXX XXXX 1111 1111 1000 0000 0000 (FF800H) To 1111 1111 1111 1111 1111 (FFFFFH) This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used Large fan-in NAND gates are not efficient Multiple NAND gate IC's might be required to perform such decoding Rather the 3-to-8 Line Decoder (74LS138) is more common. 3

Memory Systems Design & Programming CMPE 310 Memory Address Decoding The 3-to-8 Line Decoder (74LS138) Inputs Output Enable Select C B A 0 1 2 3 4 5 6 7 Select Inputs 0 G2A G2B G1 A 1 X X X X X 1 1 1 1 1 1 1 1 1 B X 1 X X X X 1 1 1 1 1 1 1 1 2 C X X 0 X X X 1 1 1 1 1 1 1 1 Outputs 3 0 0 1 0 0 0 0 1 1 1 1 1 1 1 4 0 0 1 0 0 1 1 0 1 1 1 1 1 1 G2A 0 0 1 0 1 0 1 1 0 1 1 1 1 1 5 Enable 0 0 1 0 1 1 1 1 1 0 1 1 1 1 G2B 6 0 0 1 1 0 0 1 1 1 1 0 1 1 1 G1 7 0 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively. Each output of the decoder can be attached to an 2764 EPROM ( 8K X 8 ). 4

Memory Systems Design & Programming CMPE 310 Memory Address Decoding A 0 Address Bus A 13 through A 15 select a 2764 ... A 12 A 16 through A 19 enable the decoder O 0 Data Bus ... O 7 A 13 F0000-F1FFF 0 A 2764 A 14 F2000-F3FFF 1 B (8K X 8) 74LS138 A 15 F4000-F5FFF 2 EPROM C F6000-F7FFF 3 CS F8000-F9FFF 4 CS FA000-FBFFF G2A 5 CS CS FC000-FDFFF G2B 6 A 16 CS FE000-FFFFF G1 7 CS CS CS A 17 Address space A 18 F0000H-FFFFFH A 19 RD of 8088/86 The EPROMs cover a 64KB section of memory. 5

Memory Systems Design & Programming CMPE 310 Memory Address Decoding Yet a third possibility is a PLD (Programmable Logic Device) . PLDs come in three varieties: � PLA (Programmable Logic Array) � PAL (Programmable Array Logic) � GAL (Gated Array Logic) PLDs have been around since the mid-1970s but have only recently appeared in memory systems (PALs have replaced PROM address decoders). PALs and PLAs are fuse-programmed (like the PROM). Some are erasable (like the EPROM). A PAL example (16L8) is shown in the text and is commonly used to decode the memory address, particularly for 32-bit addresses generated by the 80386DX and above. 6

Memory Systems Design & Programming CMPE 310 Memory Address Decoding AMD 16L8 PAL decoder. It has 10 fixed inputs (Pins 1-9, 11), two fixed outputs (Pins 12 and 19) and 6 pins that can be either (Pins 13-18). Programmed to decode address lines A 19 - A 13 onto 8 outputs. ;pins 1 2 3 4 5 6 7 8 9 10 A19 A18 A17 A16 A15 A14 A13 NC NC GND V CC ;pins 11 12 13 14 15 16 17 18 19 20 20 I1 1 O8 19 NC O8 O7 O6 O5 O4 O3 O2 O1 VCC I2 2 18 O7 I3 3 Equations : 17 O6 I4 4 16L8 /O1 = A19 * A18 * A17 * A16 * /A15 * /A14 * /A13 16 O5 I5 5 15 O4 /O2 = A19 * A18 * A17 * A16 * /A15 * /A14 * A13 I6 6 14 I7 7 O3 /O3 = A19 * A18 * A17 * A16 * /A15 * A14 * /A13 I8 13 8 O2 /O4 = A19 * A18 * A17 * A16 * /A15 * A14 * A13 I9 12 O1 9 /O5 = A19 * A18 * A17 * A16 * A15 * /A14 * /A13 GND I10 11 10 /O6 = A19 * A18 * A17 * A16 * A15 * /A14 * A13 /O7 = A19 * A18 * A17 * A16 * A15 * A14 * /A13 /O8 = A19 * A18 * A17 * A16 * A15 * A14 * A13 AND/NOR device with logic expressions (outputs) with up to 16 ANDed inputs and 7 ORed product terms. 7

Memory Systems Design & Programming CMPE 310 8088 and 80188 (8-bit) Memory Interface The memory systems sees the 8088 as a device with: � 20 address connections (A19 to A0). � 8 data bus connections (AD7 to AD0). � 3 control signals, IO/M, RD, and WR. We'll look at interfacing the 8088 with: � 32K of EPROM (at addresses F8000H through FFFFFH). � 512K of SRAM (at addresses 00000H through 7FFFFH). The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 ( 4K X 8 ) EPROMs. The EPROM will also require the generation of a wait state. The EPROM has an access time of 450ns . The 74LS138 requires 12ns to decode. The 8088 runs at 5MHz and only allows 460ns for memory to access data. A wait state adds 200ns of additional time. 8

Memory Systems Design & Programming CMPE 310 8088 and 80188 (8-bit) EPROM Memory Interface A 0 Address Bus To wait state generator ... A 11 WAIT O 0 Data Bus ... 74LS138 O 7 A 12 0 A 2732 A 13 1 B (4K X 8) A 14 2 C RD OE IO/ M 3 CS 4 A 15 CS G2A 5 CS A 16 CS G2B 6 A 17 CS G1 7 CS A 18 CS A 19 1K CS Address space 5V F8000H-FFFFFH The 8088 cold starts execution at FFFF0H . JMP to F8000H occurs here. 9

Memory Systems Design & Programming CMPE 310 8088 and 80188 (8-bit) RAM Memory Interface A 0 A 0 O 0 A 1 Address Bus ... ... A 8 A 14 O 7 A 2 A 9 74LS244 WE A 3 Buffer A 10 OE A 4 74LS244 A 11 A CS Buffer 74LS138 0 A 5 A 12 B (32K X 8) 1 CS A 6 62256 C 2 A 13 CS A 7 3 A 14 1G2G CS 4 G1 5 CS 1G2G 6 G2A CS 7 WR G2B CS 2 RD CS A 0 O 0 A 15 74LS244 ... ... A 16 Data Bus 3 A 14 Buffer O 7 A 17 WE OE A (32K X 8) 74LS138 CS 0 G 62256 B A 74LS138 1 BD Buffer CS 74LS245 0 1G2G C 2 B 1 CS 3 C 2 A 18 CS 4 3 G1 5 4 G1 CS 4 A 19 Dir G2A 6 5 CS G2A 7 6 G2B IO/ M G2B CS 7 CS 10

Memory Systems Design & Programming CMPE 310 8088 and 80188 (8-bit) RAM Memory Interface The 16 62256s on the previous slide are actually SRAMs. Access times are on order of 10ns . Flash memory can also be interfaced to the 8088 (see text). However, the write time ( 400ms !) is too slow to be used as RAM (as shown in the text). Parity Checking Parity checking is used to detect single bit errors in the memory. The current trend is away from parity checking. Parity checking adds 1 bit for every 8 data bits. � For EVEN parity, the 9th bit is set to yield an even number of 1's in all 9 bits. � For ODD parity, the 9th bit is set to make this number odd. For 72-pin SIMMs, the number of data bits is 32 + 4 = 36 ( 4 parity bits). 11

Memory Systems Design & Programming CMPE 310 Parity for Memory Error Detection 74AS280 Parity Generator/Checker 14 G 1 V CC Number of inputs A Outputs H 13 2 F 74AS280 thru I that are HIGH EVEN NC 12 ODD 3 E 11 I 4 D 10 0, 2, 4, 6, 8 H L C EVEN 5 ODD 9 B 6 GND 8 A 7 1, 3, 5, 7, 9 L H 9-bit parity generator/checker This circuit generates EVEN or ODD parity for the 9-bit number placed on its inputs. Typically, for generation, the 9th input bit is set to 0. This circuit also checks EVEN or ODD parity for the 9-bit number. In this case, the 9th input bit is connected to the 9th bit of memory. For example, if the original byte has an even # of 1's (with 9th bit at GND), the parity bit is set to 1 (from the EVEN output). If the EVEN output goes high during the check, then an error occurred. 12

Memory Systems Design & Programming CMPE 310 Parity for Memory Error Detection A 0 O 0 Generator Address Bus ... ... A 14 EVEN O 7 A B ODD C (32K X 8) Data Bus 62256 D 74LS280 WR E WE F OE RD G CS H I A 0 O 0 A 15 74LS138 A 0 ... ... EVEN A A 16 A 14 O 7 1 B B ODD A 17 C 2 C (32K X 8) D 3 62256 74LS280 E A 19 4 WE G1 F A 18 5 OE G G2A 6 CS IO/ M H G2B 7 I A 0 DO Checker DI ... A 15 (64K X 1) D Q 6287 74LS74 WE NMI Q CE CLK RESET Clear 13

Memory Systems Design & Programming CMPE 310 Error Detection This parity scheme can only detect a single bit error. Block-Check Character (BCC) or Checksum. Can detect multiple bit errors. This is simply the two's complement sum (the negative of the sum) of the sequence of bytes. No error occurred if adding the data values and the checksum produces a 0. For example: Given 4 hex data bytes: 10, 23, 45, 04 Check is made by adding and checking for 00 (discard the carry): Compute the sum: Invert and add 1 10 to get checksum byte: 23 10 45 0111 1100 + 1 23 04 45 1000 0011 + 1 84 04 1000 0100 = 84H 1 00 7C This is not fool proof. If 45 changes to 44 AND 04 changes to 05, the error is missed. 14