Low Power Design Thomas Ebi and Prof. Dr. J. Henkel CES - Chair for - PowerPoint PPT Presentation

1 Hardware Power Low Power Design Thomas Ebi and Prof. Dr. J. Henkel CES - Chair for Embedded Systems Karlsruhe Institute of Technology, Germany 3. Hardware power optimization and estimation http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

2 Hardware Power Overview Components consuming power hardware memory Levels of  abstraction interconnect  -system  - RTL  - gate  - transistor Tasks   Optimize (i.e. minimize for low power) Battery issues  Design / co-design (synthesize, compile, …) Estimate and  simulate OS software http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

3 Hardware Power Generic HW synthesis flow (Src: [Anand98]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

4 Hardware Power Low power HW design flow  Energy/power needs to be analyzed and optimized at each level of abstraction  Therefore, appropriate power models for each level are necessary  Shown in Fig:  a) design flow w/o energy/power  b) design flow with energy/power (Src: [Anand98]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

5 Hardware Power Power consumption in HW  A more detailed version than in the intro …     P P P P P  avg sw cap . . short circuit leakage static (Src: [Anand98])  In general, four components:  Switching capacity power  Short-circuit power  Leakage power  Static power http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

6 Hardware Power Switching capacity power  Caused by parasitic capacitors during switching: Fig. shows C_L which is the effective capacitance of all parasitic capacitances 1  Per transition:  2 P C V N f sw cap . L DD 2  Means: a) reduce operating frequency, b) reduce C_L, c) reduce voltage, d) reduce switching activity.   k C V   Most common: reduce voltage t L DD   d 2  V V  => Problem: delay of gate t_d increases too! DD th CMOS inverter (Src: [Anand98]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

7 Hardware Power Short circuit power  Explanation:  Caused by direct supply-to-ground path  When CMOS inverter in Fig. changes from 1->0 there is a short time frame within which both, nMOS and pMOS transistors are conducting => short circuit current is drawn from power supply (Src: [Anand98]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

8 Hardware Power Leakage power  Leakage can be divided into three components     P ( I I I ) Vdd leakage subthresho ld oxide diode  I diode – refers to the diodes that are formed between diffusion regions and substrate  Very small compared to the other two:  I oxide – electrons tunneling through the gate oxide  Drops off exponentially with gate length (Src: [Anand98])  ‘ off ’ transistors still conduct some current  K, S, technology parameters; W eff effective transistor channel width  NOTE: leakage power is predicted to be dominant in future silicon technologies http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

9 Hardware Power Static power  Not relevant in CMOS circuits  Note: in some literature leakage power is denoted as “ static power ”  Static power: only relevant in some nMOS circuits where there is a constant path supply-to-ground http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

10 Hardware Power Power consumption in HW: breakdown 100  Leakage power will dominate in future ( <100nm) silicon technologies Dynamic power 11  one means to reduce leakage power is to deploy dielectrics with a high k-value Subthreshold leakage Trajectory if high-k 0,01 dielectrics reach production Gateoxide leakage 10 -4 10 -6 1 1 2 2 2 2 2 time (Src: [Heer04]) 9 9 0 0 0 0 0 9 9 0 0 1 1 2 0 5 0 5 0 5 0 http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

11 Hardware Power Hardware synthesis for low power  Considered here: high-level synthesis (HLS) e.g.:  Operator scheduling  Module selection  Glitch power reduction  State transition reduction  … http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

12 Hardware Power Operator scheduling for low power  What is scheduling in the context of high-level synthesis?  Scheduling assigns operations in the behavioral description to control steps or controller states. Scheduling determines cycle-by- cycle behavior i.e. sequence in which operations are performed  Some repetition from ESI: (Src: [Anand98])  multicycling (clock period is rather short)  chaining (clock period rather long)  finding the right clock cycle time is an optimization task itself  Scheduling determines the sequence in which the various operations of the behavioral description are performed, and also dictates which operations and variables can share the same functional units and registers. Thus, scheduling can be used to enable resource sharing for low power by ensuring that correlated variables and operations with correlated operands are appropriately sequenced so that they can share the same resources http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

13 Hardware Power Operator scheduling for low power (cont ’ d)  Scheduling can be performed so as to enable maximum resource sharing between operations that belong to instances of the same computational pattern, resulting in maximal exploitation of regularity during resource sharing  Scheduling can be used to distribute the slacks or mobilities of various operations in the DFG appropriately so that some operations may be performed using slower, more energy-efficient functional units. Thus, scheduling has an impact on the power trade-offs through module selection  Scheduling determines the distribution of operations over time, and hence affects the profile of the power consumption in the implementation over time (control steps or clock cycles). Reducing peak power is important due to packaging, cooling, and reliability considerations. The effect of scheduling on peak power will be illustrated later. (Src: [Anand98])  => these tasks will be discussed in the following (some in the context of module selection) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

14 Hardware Power Operator scheduling for LP (cont ’ d)  C V  t L DD   d 2  V V t DD th d V DD Basic idea: use slack in a data flow graph (dependent upon timing constraints) and: Shown: normalized, dependency t_d = f(V_DD) a) Vary V_dd of the ALU where operator is to be executed, or (src:[Saraff95]) b) Assign operator(s) to a different ALU with a lower/higher (fixed) V_dd http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

15 Hardware Power Operator scheduling for LP (cont ’ d) Problem : Obtain a mapping of a data   : V S flow graph G=(V,E) given a base execution time t_c (or V_dd) and a timing constraint k * t_c minimize    2 ( ) i   V i such that the critical path length of the DFG is <= k * t_c  S { V V , ,..., V } c 1 c 2 ci (src:[Saraff95]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

16 Hardware Power Operator scheduling for LP (cont ’ d) - algorithm -  Step 1: initialization  Step 2: computing slack (src:[Saraff95]) l(v) – longest path of the graph that goes through node v http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

17 Hardware Power Operator scheduling for LP (cont ’ d) - algorithm -  Step 3: compute max slack value  Step 4: compute dual graph (src:[Saraff95]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

18 Hardware Power Operator scheduling for LP (cont ’ d) - algorithm -  Step 5: weight assignment  Step 6: compute longest weighted path  Step 7: reassign voltages to node in longest path (src:[Saraff95]) http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

19 Hardware Power Operator scheduling for LP (cont ’ d) - algorithm -  Step 8: go back to step 2  Conclusion Power consumption can be reduced depending on constraints up to around 25% http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13

20 Hardware Power Module selection for LP  What is module selection? The process of mapping operations from the CDFG to component templates of the RTL library  Observation: with each operation a functional unit template but not a specific instance is associated (that would be mapping)  Example: a “ + ” operation may be implemented using a  A) ripple-carry adder B) carry-lookahead adder   C) …  Ripple-carry adder is slow but more efficient in switched capacitance, carry- lookahead adder is faster but less efficient in switched capacitance  Similar tradeoffs exist in other operations  Idea: Tradeoffs can be exploited to fulfill power constraints through module selection http://ces.itec.kit.edu T. Ebi and J. Henkel, KIT, SS13