Learning Outcomes I understand the difference between level- - PowerPoint PPT Presentation

13.1 13.2 Learning Outcomes • I understand the difference between level- sensitive and edge-sensitive Unit 13 • I understand how to create an edge-triggered FF from 2 latches Sequential Logic Constructs 13.3 13.4 Sequential Logic • Suppose we have a sequence of input numbers on X[3:0] that are entered over time that we want to sum up • Possible solution: Route the outputs ________________ so we can add the current sum to the input X A0 S0 A1 How sequential building blocks work X[3:0] A2 Z[3:0] S1 9, 3, 2 14,5,2 A3 Adder BISTABLES, LATCHES, AND FLIP- B0 S2 B1 B2 S3 FLOPS B3

13.5 13.6 Sequential Logic Sequential Logic • Suppose we have a sequence of input numbers on X[3:0] that • Add logic at outputs to just capture and remember the new are entered over time that we want to sum up sum until we’re ready to input the next number in the sequence • Possible solution: Route the outputs back to the inputs so we This logic should remember (i.e. sequential logic) the sum and only can add the current sum to the input X update it when the next number arrives • Problem 1: No way to Possible Solution X0 A0 S0 Z0 _________________ X1 A1 X0 A0 S0 Z0 9, 3, 2 X2 A2 X1 A1 S1 Z1 • Problem 2: Outputs can 9, 3, 2 X2 A2 X3 A3 S1 Z1 Adder X3 A3 The data can still loop Adder _____________ to inputs and around and add up again B0 S2 Z2 B0 S2 Z2 (2+2=4) but if we just B1 be added more than once B1 hold our output = 2 then B2 B2 the feedback loop will be S3 Z3 S3 Z3 B3 per input number B3 broken We remember initial sum of 2 until input 3 arrives Outputs can feedback to at which point we’d inputs and update them capture & remember the sum more than once per sum 5. input 13.7 13.8 Sequence Adder Sequence Adder • The Reset (aka Clear) input on the FFs will cause Z to be initialized • If X changes _____________ then Z should also to 0, but then Z can’t change until the next positive edge change once per cycle • That means we will just keep adding 0 + 2 = 2 • That is why we will use ___________________ to Y0 Z0 ensure the outputs can only update once per cycle X0 A0 S0 D Q time X1 A1 2 CLR X2 A2 Y1 Z1 S1 D Q X3 A3 Clock 2 0 4-bit CLR Adder Y2 Z2 B0 S2 D Q Y0 Z0 X0 A0 S0 D Q Reset B1 CLR X1 A1 B2 Y3 Z3 CLR 0 S3 D Q X2 A2 Y1 Z1 B3 S1 D Q X 2 3 9 X3 A3 CLR 4-bit CLR Adder Y2 Z2 Clock Reset B0 S2 D Q B1 Y 2 CLR B2 Y3 Z3 S3 D Q B3 CLR Z 0 Clock Reset

13.9 13.10 Sequence Adder Sequence Adder • At the edge the flip-flops will sample the D inputs and then • Finally, at the positive edge the flip-flops will sample remember 2 until the next positive edge the D inputs and then remember 14 • That means we will just keep adding 3 + 2 = 5 Y0 Z0 Y0 Z0 X0 A0 S0 D Q X0 A0 S0 D Q time time X1 A1 X1 A1 3 CLR CLR X2 A2 Y1 Z1 X2 A2 Y1 Z1 S1 D Q S1 D Q X3 A3 X3 A3 Clock Clock 5 2 14 4-bit 4-bit CLR CLR Adder Adder Y2 Z2 Y2 Z2 B0 S2 D Q B0 S2 D Q Reset Reset B1 B1 CLR CLR Y3 Z3 Y3 Z3 B2 B2 2 S3 S3 D Q D Q B3 B3 2 3 9 2 3 9 X X CLR CLR Clock Reset Clock Reset 2 5 2 5 14 Y Y Z 0 2 Z 0 2 5 14 13.11 13.12 Sequential Logic D-Latches • But how do flip-flops work? • The primary building block of sequential logic is a D-Latch • Our first goal will be to design a circuit that • D-Latches (Data latches) store/remember/hold can remember one bit of information data when the clock is _______________ and • Easiest approach… ____ data when the clock is _______ (CLK=___) D-Latch Closed when CLK=1 D Q Q • But how do you change the input? Closed when CLK CLK=0 These "switches" which can be – A signal should only have one driver closed or open are really transistors that can be on or off

13.13 13.14 D-Latches Transparent & Hold Mode of D-Latches Hold Mode • The D-Latch operates in either C D Q Q ’ C D Q Q ’ D Q ____________ or ________ 0 x Q 0 Q 0 ’ Hold Mode 0 x Q 0 Q 0 ’ D Latch mode based on the clock value 1 0 0 1 1 0 0 1 Transparent C Q’ Mode 1 1 1 0 1 1 1 0 Function Table Description of D-Latch When Clock = 1 When Clock = 0 D D Q Q Q Q CLK CLK Transparent Mode Hold Mode (Q=D when CLK=1) (Q=Q 0 when CLK=0) 13.15 13.16 D-Latches Notation Hold Mode • To show that Q remembers its value we can put C D Q Q ’ D Q it in the past tense: Hold Mode 0 x Q 0 Q 0 ’ D Latch 1 0 0 1 Transparent – Q = Q 0 (Current Value of Q = Old Value of Q) C Q’ Mode 1 1 1 0 • OR put it in the future tense When C=0, outputs don’t change no matter what the inputs do – Q* = Q (Next Value of Q = Current Value of Q) CLK Indicates “next-value” of Q C D Q Q ’ C D Q* Q ’ * D 0 x Q 0 Q 0 ’ 0 x Q Q ’ When C=1, Q 1 0 0 1 1 0 0 1 outputs change based 1 1 1 0 1 1 1 0 on inputs Next Value = Current Value Current Value = Old Value

13.17 13.18 Adding a Sequence of Numbers Adding a Sequence of Numbers • What if we put D-Latches at the outputs • We’ll change X on every clock period Y0 Z0 X0 A0 S0 D Q X1 A1 C Y0 Z0 X2 A2 Y1 Z1 X0 A0 S0 D Q S1 D Q X3 A3 X1 A1 C Adder C X2 A2 Y1 Z1 Y2 Z2 S1 D Q X3 A3 B0 S2 D Q Adder C B1 C Y2 Z2 Clock B2 Y3 Z3 B0 S2 D Q S3 D Q B3 B1 C C X 2 3 Y3 Z3 B2 S3 D Q B3 Clock C Clock When C=0 => Q* = Q When C=1 => Q* = D 13.19 13.20 Adding a Sequence of Numbers Adding a Sequence of Numbers • Since the clock starts off low, the outputs of the • When the clock goes high the D goes through to Q latches can’t change and just hold at 0 and is free to loop back around Y0 Z0 Y0 Z0 X0 A0 S0 D Q X0 A0 S0 D Q X1 A1 C X1 A1 C 2 2 X2 A2 Y1 Z1 X2 A2 Y1 Z1 time time S1 D Q S1 D Q X3 A3 X3 A3 2 Adder C Adder C 0 2 Y2 Z2 Y2 Z2 Clock Clock B0 S2 D Q B0 S2 D Q B1 C B1 C X 2 3 X 2 3 B2 Y3 Z3 B2 Y3 Z3 S3 S3 D Q D Q B3 B3 2 C C Y 2 Y 2 Clock Clock Z 0 Z 0 2 When C=0 => Q* = Q When C=0 => Q* = Q When C=1 => Q* = D When C=1 => Q* = D

13.21 13.22 Adding a Sequence of Numbers Adding a Sequence of Numbers • Once it loops back around it will be added again, change the • This feedback loop continues until the clock goes Y value and go through to Z and loop back around again low again Y0 Z0 Y0 Z0 X0 A0 S0 D Q X0 A0 S0 D Q X1 A1 C X1 A1 C 2 2 X2 A2 Y1 Z1 X2 A2 Y1 Z1 S1 D Q time S1 D Q time X3 A3 X3 A3 Adder Adder C C 4 4 8 6 Y2 Z2 Y2 Z2 Clock Clock B0 S2 D Q B0 S2 D Q B1 C B1 C X 2 3 X 2 3 Y3 Z3 Y3 Z3 B2 B2 S3 S3 D Q D Q B3 B3 4 6 C C Y 2 4 Y 2 4 6 8 Clock Clock Z 0 2 4 Z 0 2 4 6 8 When C=0 => Q* = Q When C=0 => Q* = Q When C=1 => Q* = D When C=1 => Q* = D 13.23 13.24 Adding a Sequence of Numbers Adding a Sequence of Numbers • When the clock goes low again, the outputs will hold at their • When the clock goes high, the outputs will be free to change current value 8 until the clock goes high and we will get the feedback problem Y0 Z0 Y0 Z0 X0 A0 S0 D Q X0 A0 S0 D Q X1 A1 C X1 A1 C 3 3 X2 A2 Y1 Z1 X2 A2 Y1 Z1 time time S1 D Q S1 D Q X3 A3 X3 A3 Adder C Adder C 11 8 11 8 Y2 Z2 Y2 Z2 Clock Clock B0 S2 D Q B0 S2 D Q B1 C B1 C X 2 3 X 2 3 B2 Y3 Z3 B2 Y3 Z3 S3 S3 D Q D Q B3 B3 8 8 C C Y 2 4 6 8 11 Y 2 4 6 8 11 14 17 20 Clock Clock Z 0 2 4 6 8 Z 0 2 4 6 8 11 14 17 20 When C=0 => Q* = Q When C=0 => Q* = Q When C=1 => Q* = D When C=1 => Q* = D

13.25 13.26 Adding a Sequence of Numbers • Latches clearly don’t work • The goal should be to get one change of the outputs per clock period Y0 Z0 X0 A0 S0 D Q X1 A1 C 3 X2 A2 Y1 Z1 S1 D Q time X3 A3 Adder C 11 8 Y2 Z2 Clock B0 S2 D Q B1 C FLIP-FLOPS Y3 Z3 X 2 3 B2 S3 D Q B3 8 C Y 2 4 6 8 11 14 17 20 Clock Z 0 2 4 6 8 11 14 17 20 When C=0 => Q* = Q When C=1 => Q* = D 13.27 13.28 Flip-Flops vs. Latches Flip-Flops Flip-Flops • Change D Latches to D Flip-Flops Latches • Synchronous • Asynchronous • Clock Input • Clock/Enable input • Edge Sensitive • Level Sensitive Outputs change – – Action of the device is dependent D Q D Q only on the on the level of the clock D-FF positive D-Latch – Outputs can change anytime Q CLK (negative) edges Clock = 1 Q C Triangle at clock input indicates edge- sensitive FF D Q D Q D-Latch D-FF Q Q CLK CLK

13.29 13.30 Flip-Flops Positive-Edge Triggered D-FF • To indicate negative-edge triggered use a bubble in • Q looks at D only at CLK D Q* Q’* front of the clock input the positive-edge 0 x Q Q ’ 1 x Q Q ’ ↑ 0 0 1 ↑ Positive-Edge Triggered Negative-Edge Triggered 1 1 0 D-FF D-FF D Q D Q CLK D-FF D-FF Q Q D CLK CLK Q No bubble indicates Bubble indicates positive-edge negative-edge Q only samples D at the positive edges and then triggered triggered holds that value until the next edge 13.31 13.32 Negative-Edge Triggered D-FF D FF Example • Q looks at D only at • Assume positive edge-triggered FF CLK D Q* Q’* the negative-edge 0 x Q Q ’ 1 x Q Q ’ ↓ 0 0 1 ↓ 1 1 0 CLK D Q Q only samples D at the negative edges and then holds that value until the next edge