Laser Based Assembly of Ultra Fine Pitch Bumped ICs For - PowerPoint PPT Presentation

Laser Based Assembly of Ultra Fine Pitch Bumped ICs For Chip-to-Chip Proximity Coupled Applications Andrew Strandjord, Thorsten Teutsch, and Ghassem Azdasht Pac Tech USA – Packaging Technologies, Inc. Pac Tech USA – Packaging Technologies, Inc. Santa Clara, CA 95050 Matt Giere Sun Microsystems San Diego, CA 92121

Solder Bumping Technologies (Bump Size) Ultra Fine Pitch Micro Bumps Flip Chip WLCSP BGA Bump Size 350 µ m 150 250 200 100 300 0 0 50 50 Most Common Deposition Techniques: Paste Print, Electroplate, Sphere Drop, Sphere Transfer

Ultra Fine Pitch Bumps for: High Density Interconnects (x-y) - Close Proximity Applications (y) Die-on-Die Memory-Stacking AC/DC - Coupled Stack 3D Integration Memory-on-DSP High Speed RF Memory-Stacks Passives-on-Die Capacitive-Inductive ications Applica StatChipPAC NC State Samsung Requirements Chips and layout are different DC current to all chips Every chip the same May require RDL Close proximity Fab Backend/WLP- Solder Backend/WLP- Solder FE/Fab - TSV - TCB Cu

Chip-to-Chip Proximity Coupled Test Vehicle Properties/Requirements: Test Vehicle: 3 Chips ….. (2) Island – (1) Bridge Ultra Fine Bumps (<10 µ µ µ m) µ • FC Sized Bumps (~80 µ µ µ µ m) Island Chip • • 8 inch wafers (Island & Bridge) • Ceramic Substrate (w/cavity) Thinned Die (150 µ µ m) µ µ • • Mixed Solder Alloys Ultra Fine Pitch Pitch Bumps Bridge Chip Proximity Coupled Interconnects Island Chip 1 Island Chip 2 CSP Bumps Bridge Chip Substrate

Bridge Chip Ultra Fine Pitch Bond Pads Specifications: • 456 bond pads 40 µ 40 µ µ µ µ m bond pads µ m bond pads µ µ • • Bridge Chip Bridge Chip X: 8680 � m 30 µ µ m passivation opening µ µ • Y: 6520 � m 50 µ µ µ µ m pitch • x-y: < 5 µ µ m resolution µ µ • z: < 10 µ µ m chip-to-chip spacing Ultra Fine Pitch µ µ • Bump Area z: 150 µ µ µ µ m die thickness • Island Chip 1 Island Chip 2 Bridge Chip Substrate

Island Chip Ultra Fine Pitch Bond Pads (30 µ µ m) µ µ Ultra Fine Pitch Bump Area Island Chip (Overlap with Bridge Chip) X: 15130 � m Y: 12250 � m Flip Chip Bond Pads (70 µ µ µ m) µ Specifications: • 456 Bond Pads that match Bridge Chip 2856 Flip Chip Bumps (70 µ µ µ m pads) µ • Island Chip 1 Island Chip 2 ~ 80 µ µ µ m Bump Height µ • Bridge Chip Substrate

Three Chip Assembly + Ultra Fine Pitch Bumping Ceramic Substrate + Laser Assembly 2 High Power Island Chips 1 Low Power Bridge Chip (<10W ) Flip Chip Flip Chip Laser Assembly Bumping Proximity Coupled Communication Low Power High Bandwidth Low Noise High Density Reference: M. Giere, et.al., “Proximity Communication Flip-Chip Package with Micron Chip-to-chip Alignment Tolerances”, ECTC, Las Vegas, 2009.

Bridge Island Process Overview: 1) Deposit Ni/Au UBM (Bridge and Island) 3 µ µ µ µ m 2) Bump Bridge Die (Sn) 2-3 µ µ µ m µ Bump Island Die (SnPb) ~80 µ µ µ m µ 3) Thin & Dice Wafers 150 µ µ µ m µ 4) Die Laser Assembly (1-Bridge to 2-Island) Island Chip 1 Island Chip 2 5) Substrate Laser Assembly Bridge Chip Substrate

e-Ni/Au UBM Island Island & Bridge e-Ni/Au Process on Aluminum: 1) Passivation Clean 2) Aluminum Etch 3) Zincation I 4) Zinc Strip 5) Zincation II 6) Electroless Nickel 7) Immersion Gold Wafer Level Wet Chemical Plating Plating Batch: 50 w/hr Batch: 50 w/hr Zn II Zn II Chemistry X Control 3 µ m Ni 3 µ m Ni 600 Å Au 600 Å Au PacLine-300 ™PacTech Images are not to scale relative to each other

Ni/Au Uniformity and Adhesion 3.5 3.5 µ m) 3.3 3.3 µ Ni/Au Height above Passivaion ( µ µ µ m) µ Ni/Au Height above Al Pad ( µ µ 3.1 3.1 4 2.9 2.9 6 2.7 2.7 7 2.5 2.5 1 2 3 2.3 2.3 8 9 2.1 2.1 5 1.9 1.9 1.7 1.7 Nickel/Gold uniformity 1.5 1.5 across 8 inch wafer 0 1 2 3 4 5 6 7 8 9 10 Position On Wafer Tall Nickel Tall Nickel Average: 128.05 Max: 142.11 Shear Min: 110.42 Analysis Std: 7.121 Mode: Al Fracture 70 µ m octagonal flip chip pads

Ultra Fine Pitch Double Layer Resist Process Solder Bumping (Bridge Die) Deposit Resist 1 At IMAPS DPC 2009 reported Flood Expose 4 different technologies for lift off resist: 1) Three retro-resists 2) PMMA/Novolak stack Deposit Resist 2 Resist Pattern Expose After presentation, person from audience came up and suggested alternative 3) Use standard positive resist, coat twice, flood Develop & Descum Develop & Descum expose first layer, and expose first layer, and pattern expose second layer 3 µ m Sn LiftOff Sputter Sn Strip Resists

Tin Sputtering PE2400 3.5 4 3.3 µ m) 3.1 6 7 µ Sputtered Sn Height ( µ µ 2.9 1 2 3 2.7 8 2.5 9 2.3 5 2.1 1.9 Sn uniformity 1.7 across 8 inch wafer 1.5 0 1 2 3 4 5 6 7 8 9 10 Position On Wafer Chilled Plate Slow Sputtering Sn Features on Bridge Die after Liftoff Smooth Sn on Liftoff Resist Wrinkled Sn on Liftoff Resist

Wetability and Reflow Tests 1) Nothing happens Oven Reflow at 265-285 º C Flux and Oven Reflow Laser Reflow 2) Variable pull back Vapor Phase Reflow 3 µ µ µ µ m Sn on NiAu 3) Black film (misaligned) (misaligned) Elemental analysis shows Sn is highly oxidized Sputter thin Au layer on top of Sn (enabled by liftoff process) 500 Å

Wetability and Reflow Tests • Solder moved completely onto the pads Oven Reflow • Sn completely w/Flux converted to Sn- Ni intermetallics •Solder moved completely onto Pads Ni/Au and Sn/Au the pads • Pyramid shaped Laser Reflow No Flux => Sn has not formed excessive IMC due to short pulse laser reflow

Production Ultra SB 2 ™PacTech Flip Chip Solder Bumping (Island) 2856 bumps/die Prototyping SB 2 ™PacTech Reflow Laser Capillary Requirements: • High Yield Bumping Process • Bump Uniformity • Reliable Interconnect ~80 µ m Bump Height (100 µ m spheres) • • SnPb Eutectic

Flip Chip Bumped Die (SnPb Eutectic - 2856 bumps/die) 90 µ m) 89 Bump Height above Passivaion ( µ µ µ 88 87 86 85 84 83 82 81 Bump Height 80 Ave: 84.93 σ : 0.78 0 1 5 10 15 20 25 30 3 σ : 2.35 Position On Wafer 50 45 40 Shear Force (g) 35 30 25 20 15 10 5 Shear Force 0 Ave. 32.04 σ : 1.27 0 1 5 10 15 20 25 30 Position On Wafer Cpk: 4.46 Failure Mode: Ductile Solder

Laser Assembly LaPlace Assembly System™ PacTech 1) Pickup Die & Align ( ±5 µ m) 2) Contact (10kgf) 3) Laser Reflow 3) Laser Reflow Placement accuracy: +/- 15um: 3000 - 5000 UPH Placement accuracy: +/- 15um: 3000 - 5000 UPH Placement accuracy: +/- 10um: ~2000 UPH (20msec, Nd +3 YAG) Placement accuracy: +/- 5um: ~1000 UPH Placement accuracy: +/- 2.5um: ~500 UPH Laser based assembly allows localized heating: • Selective to individual die • Energy localized to bumped areas • Ability to differentiate between solder alloys 3) SnPb 1) Sn 2) Sn 3) SnPb • Low stress • Minimizes IMC (time/temp) Mp SnPb = 183 º C Mp Sn = 232 º C

Assembly Process Steps: 1. Pick up Bridge Chip 2. Align Bridge Chip to first Island Chip 3. Bond Bridge Chip to first Island Chip by Laser Reflow 4. Pick up bonded Bridge-Island combination 5. Align Bridge-Island assembly to second Island Chip 6. Bond Bridge-Island combination to the second Island Chip by Laser Reflow 7. Pickup three chip assembly Work In Progress 8. Align to substrate 9. Bond Island-Bridge-Island combination to substrate by Laser Reflow

Joint Integrity Tests • No Shorts Observed • No Opens Observed • Good wetting on both Bridge and Island after disassembly Island Die Bridge Die

Conclusions: • Liftoff process versatile technique for creating ultra fine pitch Sn solder bump • Au cap on Sn is essential for good wettability and reflow characteristics • Laser reflow enables assembly of ultra fine pitch Sn bumps (minimizing IMC) Ongoing Work: • Variation in laser assembly energy, pulse width, contact force,… • Substrate cavity machining (Ceramic and Laminate) Substrate cavity machining (Ceramic and Laminate) • FlipChip laser assembly to substrate • Electrical & Capacitive signal transmission analysis • Underfill studies • Cross-section analysis of solder joints and intermetallics • Variation in chip-to-chip spacing (e-Nickel thickness)